mirror of https://github.com/YosysHQ/yosys.git
synth_gatemate: Apply review remarks
* remove unused techmap models in `map_regs.v` * replace RAM initilization loops with 320-bit-writes * add script to test targets in top-level Makefile * remove `MAXWIDTH` parameter and treat both vector widths individually in `mult_map.v` * iterate over all modules in `gatemate_bramopt` pass
This commit is contained in:
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1
Makefile
1
Makefile
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@ -814,6 +814,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
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+cd tests/arch/intel_alm && bash run-test.sh $(SEEDOPT)
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+cd tests/arch/nexus && bash run-test.sh $(SEEDOPT)
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+cd tests/arch/quicklogic && bash run-test.sh $(SEEDOPT)
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+cd tests/arch/gatemate && bash run-test.sh $(SEEDOPT)
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+cd tests/rpc && bash run-test.sh
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+cd tests/memfile && bash run-test.sh
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+cd tests/verilog && bash run-test.sh
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@ -294,7 +294,7 @@ module CC_DFF #(
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assign en = (EN_INV) ? ~EN : EN;
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assign sr = (SR_INV) ? ~SR : SR;
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initial Q = 1'bX;
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initial Q = 1'b0;
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always @(posedge clk or posedge sr)
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begin
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@ -323,7 +323,7 @@ module CC_DLT #(
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assign en = (G_INV) ? ~G : G;
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assign sr = (SR_INV) ? ~SR : SR;
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initial Q = 1'bX;
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initial Q = 1'b0;
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always @(*)
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begin
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@ -675,72 +675,70 @@ module CC_BRAM_20K (
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$finish();
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end
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// RAM initialization
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for (i=0; i < 320; i=i+1) begin
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memory[320*0+i] = INIT_00[i];
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memory[320*1+i] = INIT_01[i];
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memory[320*2+i] = INIT_02[i];
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memory[320*3+i] = INIT_03[i];
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memory[320*4+i] = INIT_04[i];
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memory[320*5+i] = INIT_05[i];
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memory[320*6+i] = INIT_06[i];
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memory[320*7+i] = INIT_07[i];
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memory[320*8+i] = INIT_08[i];
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memory[320*9+i] = INIT_09[i];
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memory[320*10+i] = INIT_0A[i];
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memory[320*11+i] = INIT_0B[i];
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memory[320*12+i] = INIT_0C[i];
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memory[320*13+i] = INIT_0D[i];
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memory[320*14+i] = INIT_0E[i];
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memory[320*15+i] = INIT_0F[i];
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memory[320*16+i] = INIT_10[i];
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memory[320*17+i] = INIT_11[i];
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memory[320*18+i] = INIT_12[i];
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memory[320*19+i] = INIT_13[i];
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memory[320*20+i] = INIT_14[i];
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memory[320*21+i] = INIT_15[i];
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memory[320*22+i] = INIT_16[i];
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memory[320*23+i] = INIT_17[i];
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memory[320*24+i] = INIT_18[i];
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memory[320*25+i] = INIT_19[i];
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memory[320*26+i] = INIT_1A[i];
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memory[320*27+i] = INIT_1B[i];
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memory[320*28+i] = INIT_1C[i];
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memory[320*29+i] = INIT_1D[i];
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memory[320*30+i] = INIT_1E[i];
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memory[320*31+i] = INIT_1F[i];
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memory[320*32+i] = INIT_20[i];
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memory[320*33+i] = INIT_21[i];
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memory[320*34+i] = INIT_22[i];
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memory[320*35+i] = INIT_23[i];
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memory[320*36+i] = INIT_24[i];
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memory[320*37+i] = INIT_25[i];
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memory[320*38+i] = INIT_26[i];
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memory[320*39+i] = INIT_27[i];
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memory[320*30+i] = INIT_28[i];
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memory[320*41+i] = INIT_29[i];
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memory[320*42+i] = INIT_2A[i];
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memory[320*43+i] = INIT_2B[i];
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memory[320*44+i] = INIT_2C[i];
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memory[320*45+i] = INIT_2D[i];
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memory[320*46+i] = INIT_2E[i];
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memory[320*47+i] = INIT_2F[i];
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memory[320*48+i] = INIT_30[i];
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memory[320*49+i] = INIT_31[i];
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memory[320*50+i] = INIT_32[i];
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memory[320*51+i] = INIT_33[i];
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memory[320*52+i] = INIT_34[i];
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memory[320*53+i] = INIT_35[i];
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memory[320*54+i] = INIT_36[i];
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memory[320*55+i] = INIT_37[i];
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memory[320*56+i] = INIT_38[i];
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memory[320*57+i] = INIT_39[i];
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memory[320*58+i] = INIT_3A[i];
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memory[320*59+i] = INIT_3B[i];
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memory[320*60+i] = INIT_3C[i];
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memory[320*61+i] = INIT_3D[i];
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memory[320*62+i] = INIT_3E[i];
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memory[320*63+i] = INIT_3F[i];
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end
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memory[320*0+319:320*0] = INIT_00;
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memory[320*1+319:320*1] = INIT_01;
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memory[320*2+319:320*2] = INIT_02;
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memory[320*3+319:320*3] = INIT_03;
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memory[320*4+319:320*4] = INIT_04;
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memory[320*5+319:320*5] = INIT_05;
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memory[320*6+319:320*6] = INIT_06;
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memory[320*7+319:320*7] = INIT_07;
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memory[320*8+319:320*8] = INIT_08;
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memory[320*9+319:320*9] = INIT_09;
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memory[320*10+319:320*10] = INIT_0A;
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memory[320*11+319:320*11] = INIT_0B;
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memory[320*12+319:320*12] = INIT_0C;
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memory[320*13+319:320*13] = INIT_0D;
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memory[320*14+319:320*14] = INIT_0E;
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memory[320*15+319:320*15] = INIT_0F;
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memory[320*16+319:320*16] = INIT_10;
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memory[320*17+319:320*17] = INIT_11;
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memory[320*18+319:320*18] = INIT_12;
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memory[320*19+319:320*19] = INIT_13;
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memory[320*20+319:320*20] = INIT_14;
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memory[320*21+319:320*21] = INIT_15;
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memory[320*22+319:320*22] = INIT_16;
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memory[320*23+319:320*23] = INIT_17;
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memory[320*24+319:320*24] = INIT_18;
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memory[320*25+319:320*25] = INIT_19;
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memory[320*26+319:320*26] = INIT_1A;
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memory[320*27+319:320*27] = INIT_1B;
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memory[320*28+319:320*28] = INIT_1C;
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memory[320*29+319:320*29] = INIT_1D;
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memory[320*30+319:320*30] = INIT_1E;
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memory[320*31+319:320*31] = INIT_1F;
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memory[320*32+319:320*32] = INIT_20;
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memory[320*33+319:320*33] = INIT_21;
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memory[320*34+319:320*34] = INIT_22;
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memory[320*35+319:320*35] = INIT_23;
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memory[320*36+319:320*36] = INIT_24;
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memory[320*37+319:320*37] = INIT_25;
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memory[320*38+319:320*38] = INIT_26;
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memory[320*39+319:320*39] = INIT_27;
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memory[320*40+319:320*40] = INIT_28;
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memory[320*41+319:320*41] = INIT_29;
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memory[320*42+319:320*42] = INIT_2A;
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memory[320*43+319:320*43] = INIT_2B;
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memory[320*44+319:320*44] = INIT_2C;
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memory[320*45+319:320*45] = INIT_2D;
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memory[320*46+319:320*46] = INIT_2E;
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memory[320*47+319:320*47] = INIT_2F;
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memory[320*48+319:320*48] = INIT_30;
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memory[320*49+319:320*49] = INIT_31;
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memory[320*50+319:320*50] = INIT_32;
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memory[320*51+319:320*51] = INIT_33;
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memory[320*52+319:320*52] = INIT_34;
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memory[320*53+319:320*53] = INIT_35;
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memory[320*54+319:320*54] = INIT_36;
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memory[320*55+319:320*55] = INIT_37;
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memory[320*56+319:320*56] = INIT_38;
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memory[320*57+319:320*57] = INIT_39;
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memory[320*58+319:320*58] = INIT_3A;
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memory[320*59+319:320*59] = INIT_3B;
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memory[320*60+319:320*60] = INIT_3C;
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memory[320*61+319:320*61] = INIT_3D;
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memory[320*62+319:320*62] = INIT_3E;
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memory[320*63+319:320*63] = INIT_3F;
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end
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// Signal inversion
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@ -1163,136 +1161,134 @@ module CC_BRAM_40K (
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$finish();
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end
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// RAM initialization
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for (i=0; i < 320; i=i+1) begin
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memory[320*0+i] = INIT_00[i];
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memory[320*1+i] = INIT_01[i];
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memory[320*2+i] = INIT_02[i];
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memory[320*3+i] = INIT_03[i];
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memory[320*4+i] = INIT_04[i];
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memory[320*5+i] = INIT_05[i];
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memory[320*6+i] = INIT_06[i];
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memory[320*7+i] = INIT_07[i];
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memory[320*8+i] = INIT_08[i];
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memory[320*9+i] = INIT_09[i];
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memory[320*10+i] = INIT_0A[i];
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memory[320*11+i] = INIT_0B[i];
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memory[320*12+i] = INIT_0C[i];
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memory[320*13+i] = INIT_0D[i];
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memory[320*14+i] = INIT_0E[i];
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memory[320*15+i] = INIT_0F[i];
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memory[320*16+i] = INIT_10[i];
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memory[320*17+i] = INIT_11[i];
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memory[320*18+i] = INIT_12[i];
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memory[320*19+i] = INIT_13[i];
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memory[320*20+i] = INIT_14[i];
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memory[320*21+i] = INIT_15[i];
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memory[320*22+i] = INIT_16[i];
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memory[320*23+i] = INIT_17[i];
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memory[320*24+i] = INIT_18[i];
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memory[320*25+i] = INIT_19[i];
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memory[320*26+i] = INIT_1A[i];
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memory[320*27+i] = INIT_1B[i];
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memory[320*28+i] = INIT_1C[i];
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memory[320*29+i] = INIT_1D[i];
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memory[320*30+i] = INIT_1E[i];
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memory[320*31+i] = INIT_1F[i];
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memory[320*32+i] = INIT_20[i];
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memory[320*33+i] = INIT_21[i];
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memory[320*34+i] = INIT_22[i];
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memory[320*35+i] = INIT_23[i];
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memory[320*36+i] = INIT_24[i];
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memory[320*37+i] = INIT_25[i];
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memory[320*38+i] = INIT_26[i];
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memory[320*39+i] = INIT_27[i];
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memory[320*30+i] = INIT_28[i];
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memory[320*41+i] = INIT_29[i];
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memory[320*42+i] = INIT_2A[i];
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memory[320*43+i] = INIT_2B[i];
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memory[320*44+i] = INIT_2C[i];
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memory[320*45+i] = INIT_2D[i];
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memory[320*46+i] = INIT_2E[i];
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memory[320*47+i] = INIT_2F[i];
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memory[320*48+i] = INIT_30[i];
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memory[320*49+i] = INIT_31[i];
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memory[320*50+i] = INIT_32[i];
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memory[320*51+i] = INIT_33[i];
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memory[320*52+i] = INIT_34[i];
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memory[320*53+i] = INIT_35[i];
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memory[320*54+i] = INIT_36[i];
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memory[320*55+i] = INIT_37[i];
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memory[320*56+i] = INIT_38[i];
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memory[320*57+i] = INIT_39[i];
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memory[320*58+i] = INIT_3A[i];
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memory[320*59+i] = INIT_3B[i];
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memory[320*60+i] = INIT_3C[i];
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memory[320*61+i] = INIT_3D[i];
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memory[320*62+i] = INIT_3E[i];
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memory[320*63+i] = INIT_3F[i];
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memory[320*64+i] = INIT_40[i];
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memory[320*65+i] = INIT_41[i];
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memory[320*66+i] = INIT_42[i];
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memory[320*67+i] = INIT_43[i];
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memory[320*68+i] = INIT_44[i];
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memory[320*69+i] = INIT_45[i];
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memory[320*70+i] = INIT_46[i];
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memory[320*71+i] = INIT_47[i];
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memory[320*72+i] = INIT_48[i];
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memory[320*73+i] = INIT_49[i];
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memory[320*74+i] = INIT_4A[i];
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memory[320*75+i] = INIT_4B[i];
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memory[320*76+i] = INIT_4C[i];
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memory[320*77+i] = INIT_4D[i];
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memory[320*78+i] = INIT_4E[i];
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memory[320*79+i] = INIT_4F[i];
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memory[320*80+i] = INIT_50[i];
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memory[320*81+i] = INIT_51[i];
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memory[320*82+i] = INIT_52[i];
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memory[320*83+i] = INIT_53[i];
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memory[320*84+i] = INIT_54[i];
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memory[320*85+i] = INIT_55[i];
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memory[320*86+i] = INIT_56[i];
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memory[320*87+i] = INIT_57[i];
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memory[320*88+i] = INIT_58[i];
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memory[320*89+i] = INIT_59[i];
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memory[320*90+i] = INIT_5A[i];
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memory[320*91+i] = INIT_5B[i];
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memory[320*92+i] = INIT_5C[i];
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memory[320*93+i] = INIT_5D[i];
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memory[320*94+i] = INIT_5E[i];
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memory[320*95+i] = INIT_5F[i];
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memory[320*96+i] = INIT_60[i];
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memory[320*97+i] = INIT_61[i];
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memory[320*98+i] = INIT_62[i];
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memory[320*99+i] = INIT_63[i];
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memory[320*100+i] = INIT_64[i];
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memory[320*101+i] = INIT_65[i];
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memory[320*102+i] = INIT_66[i];
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memory[320*103+i] = INIT_67[i];
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memory[320*104+i] = INIT_68[i];
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memory[320*105+i] = INIT_69[i];
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memory[320*106+i] = INIT_6A[i];
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memory[320*107+i] = INIT_6B[i];
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memory[320*108+i] = INIT_6C[i];
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memory[320*109+i] = INIT_6D[i];
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memory[320*110+i] = INIT_6E[i];
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memory[320*111+i] = INIT_6F[i];
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memory[320*112+i] = INIT_70[i];
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memory[320*113+i] = INIT_71[i];
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memory[320*114+i] = INIT_72[i];
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memory[320*115+i] = INIT_73[i];
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memory[320*116+i] = INIT_74[i];
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memory[320*117+i] = INIT_75[i];
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memory[320*118+i] = INIT_76[i];
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memory[320*119+i] = INIT_77[i];
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memory[320*120+i] = INIT_78[i];
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memory[320*121+i] = INIT_79[i];
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memory[320*122+i] = INIT_7A[i];
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memory[320*123+i] = INIT_7B[i];
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memory[320*124+i] = INIT_7C[i];
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memory[320*125+i] = INIT_7D[i];
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memory[320*126+i] = INIT_7E[i];
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memory[320*127+i] = INIT_7F[i];
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end
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memory[320*0+319:320*0] = INIT_00;
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memory[320*1+319:320*1] = INIT_01;
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memory[320*2+319:320*2] = INIT_02;
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memory[320*3+319:320*3] = INIT_03;
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memory[320*4+319:320*4] = INIT_04;
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memory[320*5+319:320*5] = INIT_05;
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memory[320*6+319:320*6] = INIT_06;
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memory[320*7+319:320*7] = INIT_07;
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memory[320*8+319:320*8] = INIT_08;
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memory[320*9+319:320*9] = INIT_09;
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memory[320*10+319:320*10] = INIT_0A;
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memory[320*11+319:320*11] = INIT_0B;
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memory[320*12+319:320*12] = INIT_0C;
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memory[320*13+319:320*13] = INIT_0D;
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memory[320*14+319:320*14] = INIT_0E;
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memory[320*15+319:320*15] = INIT_0F;
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memory[320*16+319:320*16] = INIT_10;
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memory[320*17+319:320*17] = INIT_11;
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memory[320*18+319:320*18] = INIT_12;
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memory[320*19+319:320*19] = INIT_13;
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memory[320*20+319:320*20] = INIT_14;
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memory[320*21+319:320*21] = INIT_15;
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memory[320*22+319:320*22] = INIT_16;
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memory[320*23+319:320*23] = INIT_17;
|
||||
memory[320*24+319:320*24] = INIT_18;
|
||||
memory[320*25+319:320*25] = INIT_19;
|
||||
memory[320*26+319:320*26] = INIT_1A;
|
||||
memory[320*27+319:320*27] = INIT_1B;
|
||||
memory[320*28+319:320*28] = INIT_1C;
|
||||
memory[320*29+319:320*29] = INIT_1D;
|
||||
memory[320*30+319:320*30] = INIT_1E;
|
||||
memory[320*31+319:320*31] = INIT_1F;
|
||||
memory[320*32+319:320*32] = INIT_20;
|
||||
memory[320*33+319:320*33] = INIT_21;
|
||||
memory[320*34+319:320*34] = INIT_22;
|
||||
memory[320*35+319:320*35] = INIT_23;
|
||||
memory[320*36+319:320*36] = INIT_24;
|
||||
memory[320*37+319:320*37] = INIT_25;
|
||||
memory[320*38+319:320*38] = INIT_26;
|
||||
memory[320*39+319:320*39] = INIT_27;
|
||||
memory[320*40+319:320*40] = INIT_28;
|
||||
memory[320*41+319:320*41] = INIT_29;
|
||||
memory[320*42+319:320*42] = INIT_2A;
|
||||
memory[320*43+319:320*43] = INIT_2B;
|
||||
memory[320*44+319:320*44] = INIT_2C;
|
||||
memory[320*45+319:320*45] = INIT_2D;
|
||||
memory[320*46+319:320*46] = INIT_2E;
|
||||
memory[320*47+319:320*47] = INIT_2F;
|
||||
memory[320*48+319:320*48] = INIT_30;
|
||||
memory[320*49+319:320*49] = INIT_31;
|
||||
memory[320*50+319:320*50] = INIT_32;
|
||||
memory[320*51+319:320*51] = INIT_33;
|
||||
memory[320*52+319:320*52] = INIT_34;
|
||||
memory[320*53+319:320*53] = INIT_35;
|
||||
memory[320*54+319:320*54] = INIT_36;
|
||||
memory[320*55+319:320*55] = INIT_37;
|
||||
memory[320*56+319:320*56] = INIT_38;
|
||||
memory[320*57+319:320*57] = INIT_39;
|
||||
memory[320*58+319:320*58] = INIT_3A;
|
||||
memory[320*59+319:320*59] = INIT_3B;
|
||||
memory[320*60+319:320*60] = INIT_3C;
|
||||
memory[320*61+319:320*61] = INIT_3D;
|
||||
memory[320*62+319:320*62] = INIT_3E;
|
||||
memory[320*63+319:320*63] = INIT_3F;
|
||||
memory[320*64+319:320*64] = INIT_40;
|
||||
memory[320*65+319:320*65] = INIT_41;
|
||||
memory[320*66+319:320*66] = INIT_42;
|
||||
memory[320*67+319:320*67] = INIT_43;
|
||||
memory[320*68+319:320*68] = INIT_44;
|
||||
memory[320*69+319:320*69] = INIT_45;
|
||||
memory[320*70+319:320*70] = INIT_46;
|
||||
memory[320*71+319:320*71] = INIT_47;
|
||||
memory[320*72+319:320*72] = INIT_48;
|
||||
memory[320*73+319:320*73] = INIT_49;
|
||||
memory[320*74+319:320*74] = INIT_4A;
|
||||
memory[320*75+319:320*75] = INIT_4B;
|
||||
memory[320*76+319:320*76] = INIT_4C;
|
||||
memory[320*77+319:320*77] = INIT_4D;
|
||||
memory[320*78+319:320*78] = INIT_4E;
|
||||
memory[320*79+319:320*79] = INIT_4F;
|
||||
memory[320*80+319:320*80] = INIT_50;
|
||||
memory[320*81+319:320*81] = INIT_51;
|
||||
memory[320*82+319:320*82] = INIT_52;
|
||||
memory[320*83+319:320*83] = INIT_53;
|
||||
memory[320*84+319:320*84] = INIT_54;
|
||||
memory[320*85+319:320*85] = INIT_55;
|
||||
memory[320*86+319:320*86] = INIT_56;
|
||||
memory[320*87+319:320*87] = INIT_57;
|
||||
memory[320*88+319:320*88] = INIT_58;
|
||||
memory[320*89+319:320*89] = INIT_59;
|
||||
memory[320*90+319:320*90] = INIT_5A;
|
||||
memory[320*91+319:320*91] = INIT_5B;
|
||||
memory[320*92+319:320*92] = INIT_5C;
|
||||
memory[320*93+319:320*93] = INIT_5D;
|
||||
memory[320*94+319:320*94] = INIT_5E;
|
||||
memory[320*95+319:320*95] = INIT_5F;
|
||||
memory[320*96+319:320*96] = INIT_60;
|
||||
memory[320*97+319:320*97] = INIT_61;
|
||||
memory[320*98+319:320*98] = INIT_62;
|
||||
memory[320*99+319:320*99] = INIT_63;
|
||||
memory[320*100+319:320*100] = INIT_64;
|
||||
memory[320*101+319:320*101] = INIT_65;
|
||||
memory[320*102+319:320*102] = INIT_66;
|
||||
memory[320*103+319:320*103] = INIT_67;
|
||||
memory[320*104+319:320*104] = INIT_68;
|
||||
memory[320*105+319:320*105] = INIT_69;
|
||||
memory[320*106+319:320*106] = INIT_6A;
|
||||
memory[320*107+319:320*107] = INIT_6B;
|
||||
memory[320*108+319:320*108] = INIT_6C;
|
||||
memory[320*109+319:320*109] = INIT_6D;
|
||||
memory[320*110+319:320*110] = INIT_6E;
|
||||
memory[320*111+319:320*111] = INIT_6F;
|
||||
memory[320*112+319:320*112] = INIT_70;
|
||||
memory[320*113+319:320*113] = INIT_71;
|
||||
memory[320*114+319:320*114] = INIT_72;
|
||||
memory[320*115+319:320*115] = INIT_73;
|
||||
memory[320*116+319:320*116] = INIT_74;
|
||||
memory[320*117+319:320*117] = INIT_75;
|
||||
memory[320*118+319:320*118] = INIT_76;
|
||||
memory[320*119+319:320*119] = INIT_77;
|
||||
memory[320*120+319:320*120] = INIT_78;
|
||||
memory[320*121+319:320*121] = INIT_79;
|
||||
memory[320*122+319:320*122] = INIT_7A;
|
||||
memory[320*123+319:320*123] = INIT_7B;
|
||||
memory[320*124+319:320*124] = INIT_7C;
|
||||
memory[320*125+319:320*125] = INIT_7D;
|
||||
memory[320*126+319:320*126] = INIT_7E;
|
||||
memory[320*127+319:320*127] = INIT_7F;
|
||||
end
|
||||
|
||||
// Signal inversion
|
||||
|
|
|
@ -134,15 +134,11 @@ struct GateMateBramOptPass : public Pass {
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
Module *module = design->top_module();
|
||||
|
||||
if (module == nullptr)
|
||||
for (auto module : design->selected_modules())
|
||||
{
|
||||
log_cmd_error("No top module found.\n");
|
||||
}
|
||||
|
||||
if (!noglwren) {
|
||||
proc_glwren(module);
|
||||
if (!noglwren) {
|
||||
proc_glwren(module);
|
||||
}
|
||||
}
|
||||
}
|
||||
} GateMateBramOptPass;
|
||||
|
|
|
@ -36,27 +36,28 @@ module \$__MULMXN (A, B, Y);
|
|||
(* force_downto *)
|
||||
output [Y_WIDTH-1:0] Y;
|
||||
|
||||
localparam MAXWIDTH = `MAX(A_WIDTH, B_WIDTH) + ((A_SIGNED || B_SIGNED) ? 0 : 1);
|
||||
localparam A_MAXWIDTH = A_WIDTH + (A_SIGNED ? 0 : 1);
|
||||
localparam B_MAXWIDTH = B_WIDTH + (B_SIGNED ? 0 : 1);
|
||||
|
||||
generate
|
||||
if (A_SIGNED) begin: blkA
|
||||
wire signed [MAXWIDTH-1:0] Aext = $signed(A);
|
||||
wire signed [A_MAXWIDTH-1:0] Aext = $signed(A);
|
||||
end
|
||||
else begin: blkA
|
||||
wire [MAXWIDTH-1:0] Aext = A;
|
||||
wire [A_MAXWIDTH-1:0] Aext = A;
|
||||
end
|
||||
if (B_SIGNED) begin: blkB
|
||||
wire signed [MAXWIDTH-1:0] Bext = $signed(B);
|
||||
wire signed [B_MAXWIDTH-1:0] Bext = $signed(B);
|
||||
end
|
||||
else begin: blkB
|
||||
wire [MAXWIDTH-1:0] Bext = B;
|
||||
wire [B_MAXWIDTH-1:0] Bext = B;
|
||||
end
|
||||
|
||||
if (A_WIDTH >= B_WIDTH) begin
|
||||
CC_MULT #(
|
||||
.A_WIDTH(MAXWIDTH),
|
||||
.B_WIDTH(MAXWIDTH),
|
||||
.P_WIDTH(`MIN(Y_WIDTH,MAXWIDTH+MAXWIDTH)),
|
||||
.A_WIDTH(A_MAXWIDTH),
|
||||
.B_WIDTH(B_MAXWIDTH),
|
||||
.P_WIDTH(Y_WIDTH),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.A(blkA.Aext),
|
||||
.B(blkB.Bext),
|
||||
|
@ -65,9 +66,9 @@ module \$__MULMXN (A, B, Y);
|
|||
end
|
||||
else begin // swap A,B
|
||||
CC_MULT #(
|
||||
.A_WIDTH(MAXWIDTH),
|
||||
.B_WIDTH(MAXWIDTH),
|
||||
.P_WIDTH(`MIN(Y_WIDTH,MAXWIDTH+MAXWIDTH)),
|
||||
.A_WIDTH(A_MAXWIDTH),
|
||||
.B_WIDTH(B_MAXWIDTH),
|
||||
.P_WIDTH(Y_WIDTH),
|
||||
) _TECHMAP_REPLACE_ (
|
||||
.A(blkB.Bext),
|
||||
.B(blkA.Aext),
|
||||
|
|
|
@ -17,54 +17,6 @@
|
|||
*
|
||||
*/
|
||||
|
||||
(* techmap_celltype = "$_DFF_[NP]_" *)
|
||||
module \$_DFF_x_ (input D, C, output Q);
|
||||
|
||||
parameter _TECHMAP_CELLTYPE_ = "";
|
||||
|
||||
CC_DFF #(
|
||||
.CLK_INV((_TECHMAP_CELLTYPE_[15:8] == "N")),
|
||||
.EN_INV(1'b0),
|
||||
.SR_INV(1'b0),
|
||||
.SR_VAL(1'b0)
|
||||
) _TECHMAP_REPLACE_ (.D(D), .EN(1'b1), .CLK(C), .SR(1'b0), .Q(Q));
|
||||
|
||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
||||
|
||||
endmodule
|
||||
|
||||
(* techmap_celltype = "$_DFF_[NP][NP][01]_" *)
|
||||
module \$_DFF_xxx_ (input D, C, R, output Q);
|
||||
|
||||
parameter _TECHMAP_CELLTYPE_ = "";
|
||||
|
||||
CC_DFF #(
|
||||
.CLK_INV(_TECHMAP_CELLTYPE_[31:24] == "N"),
|
||||
.EN_INV(1'b0),
|
||||
.SR_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
|
||||
.SR_VAL(_TECHMAP_CELLTYPE_[15:8] == "1")
|
||||
) _TECHMAP_REPLACE_ (.D(D), .EN(1'b1), .CLK(C), .SR(R), .Q(Q));
|
||||
|
||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
||||
|
||||
endmodule
|
||||
|
||||
(* techmap_celltype = "$_DFFE_[NP][NP]_" *)
|
||||
module \$_DFFE_xx_ (input D, C, E, output Q);
|
||||
|
||||
parameter _TECHMAP_CELLTYPE_ = "";
|
||||
|
||||
CC_DFF #(
|
||||
.CLK_INV(_TECHMAP_CELLTYPE_[23:16] == "N"),
|
||||
.EN_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
|
||||
.SR_INV(1'b0),
|
||||
.SR_VAL(1'b0)
|
||||
) _TECHMAP_REPLACE_ (.D(D), .EN(E), .CLK(C), .SR(1'b0), .Q(Q));
|
||||
|
||||
wire _TECHMAP_REMOVEINIT_Q_ = 1'b1;
|
||||
|
||||
endmodule
|
||||
|
||||
(* techmap_celltype = "$_DFFE_[NP][NP][01][NP]_" *)
|
||||
module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
|
||||
|
||||
|
@ -81,19 +33,6 @@ module \$_DFFE_xxxx_ (input D, C, R, E, output Q);
|
|||
|
||||
endmodule
|
||||
|
||||
(* techmap_celltype = "$_DLATCH_[NP]_" *)
|
||||
module \$_DLATCH_x_ (input E, D, output Q);
|
||||
|
||||
parameter _TECHMAP_CELLTYPE_ = "";
|
||||
|
||||
CC_DLT #(
|
||||
.G_INV(_TECHMAP_CELLTYPE_[15:8] == "N"),
|
||||
.SR_INV(1'b0),
|
||||
.SR_VAL(1'b0)
|
||||
) _TECHMAP_REPLACE_ (.D(D), .G(E), .SR(1'b0), .Q(Q));
|
||||
|
||||
endmodule
|
||||
|
||||
(* techmap_celltype = "$_DLATCH_[NP][NP][01]_" *)
|
||||
module \$_DLATCH_xxx_ (input E, R, D, output Q);
|
||||
|
||||
|
|
|
@ -305,7 +305,7 @@ struct SynthGateMatePass : public ScriptPass
|
|||
if (check_label("map_regs"))
|
||||
{
|
||||
run("opt_clean");
|
||||
run("dfflegalize -cell $_DFFE_????_ x -cell $_DLATCH_???_ x");
|
||||
run("dfflegalize -cell $_DFFE_????_ 0 -cell $_DLATCH_???_ 0");
|
||||
run("techmap -map +/gatemate/reg_map.v");
|
||||
run("opt_expr -mux_undef");
|
||||
run("simplemap");
|
||||
|
|
Loading…
Reference in New Issue