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Changed LEVEL resets for GP_COUNTx to be properly synthesizeable

This commit is contained in:
Andrew Zonenberg 2017-08-07 20:42:19 -07:00
parent 9f3dc59ffe
commit 0a6c702c41
1 changed files with 60 additions and 48 deletions
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72
techlibs/greenpak4/cells_sim_digital.v
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@ -57,7 +57,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
case(RESET_MODE) case(RESET_MODE)
"RISING": begin "RISING": begin
always @(posedge CLK or posedge RST) begin always @(posedge CLK, posedge RST) begin
count <= count - 1'd1; count <= count - 1'd1;
if(count == 0) if(count == 0)
count <= COUNT_TO; count <= COUNT_TO;
@ -68,7 +68,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
end end
"FALLING": begin "FALLING": begin
always @(posedge CLK or negedge RST) begin always @(posedge CLK, negedge RST) begin
count <= count - 1'd1; count <= count - 1'd1;
if(count == 0) if(count == 0)
count <= COUNT_TO; count <= COUNT_TO;
@ -86,13 +86,15 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
end end
"LEVEL": begin "LEVEL": begin
always @(posedge CLK or posedge RST) begin always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1; count <= count - 1'd1;
if(count == 0) if(count == 0)
count <= COUNT_TO; count <= COUNT_TO;
end
if(RST)
count <= 0;
end end
end end
@ -141,7 +143,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
case(RESET_MODE) case(RESET_MODE)
"RISING": begin "RISING": begin
always @(posedge CLK or posedge RST) begin always @(posedge CLK, posedge RST) begin
//Main counter //Main counter
if(KEEP) begin if(KEEP) begin
@ -169,7 +171,7 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
end end
"FALLING": begin "FALLING": begin
always @(posedge CLK or negedge RST) begin always @(posedge CLK, negedge RST) begin
//Main counter //Main counter
if(KEEP) begin if(KEEP) begin
@ -204,7 +206,17 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
end end
"LEVEL": begin "LEVEL": begin
always @(posedge CLK or posedge RST) begin always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else begin
//Main counter //Main counter
if(KEEP) begin if(KEEP) begin
@ -220,12 +232,6 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
if(count == 14'h3fff && UP) if(count == 14'h3fff && UP)
count <= COUNT_TO; count <= COUNT_TO;
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end end
end end
@ -276,7 +282,7 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
case(RESET_MODE) case(RESET_MODE)
"RISING": begin "RISING": begin
always @(posedge CLK or posedge RST) begin always @(posedge CLK, posedge RST) begin
//Main counter //Main counter
if(KEEP) begin if(KEEP) begin
@ -304,7 +310,7 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
end end
"FALLING": begin "FALLING": begin
always @(posedge CLK or negedge RST) begin always @(posedge CLK, negedge RST) begin
//Main counter //Main counter
if(KEEP) begin if(KEEP) begin
@ -339,7 +345,17 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
end end
"LEVEL": begin "LEVEL": begin
always @(posedge CLK or posedge RST) begin always @(posedge CLK, posedge RST) begin
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end
else begin
//Main counter //Main counter
if(KEEP) begin if(KEEP) begin
@ -355,12 +371,6 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
if(count == 8'hff && UP) if(count == 8'hff && UP)
count <= COUNT_TO; count <= COUNT_TO;
//Resets
if(RST) begin
if(RESET_VALUE == "ZERO")
count <= 0;
else
count <= COUNT_TO;
end end
end end
@ -410,7 +420,7 @@ module GP_COUNT8(
case(RESET_MODE) case(RESET_MODE)
"RISING": begin "RISING": begin
always @(posedge CLK or posedge RST) begin always @(posedge CLK, posedge RST) begin
count <= count - 1'd1; count <= count - 1'd1;
if(count == 0) if(count == 0)
count <= COUNT_TO; count <= COUNT_TO;
@ -421,7 +431,7 @@ module GP_COUNT8(
end end
"FALLING": begin "FALLING": begin
always @(posedge CLK or negedge RST) begin always @(posedge CLK, negedge RST) begin
count <= count - 1'd1; count <= count - 1'd1;
if(count == 0) if(count == 0)
count <= COUNT_TO; count <= COUNT_TO;
@ -439,13 +449,15 @@ module GP_COUNT8(
end end
"LEVEL": begin "LEVEL": begin
always @(posedge CLK or posedge RST) begin always @(posedge CLK, posedge RST) begin
if(RST)
count <= 0;
else begin
count <= count - 1'd1; count <= count - 1'd1;
if(count == 0) if(count == 0)
count <= COUNT_TO; count <= COUNT_TO;
end
if(RST)
count <= 0;
end end
end end