mirror of https://github.com/YosysHQ/yosys.git
Fix and_or_buffer optimization in opt_expr for signed operators
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@ -371,13 +371,13 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
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if (cell->type.in("$reduce_and", "$_AND_"))
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if (cell->type.in("$reduce_and", "$_AND_"))
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detect_const_and = true;
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detect_const_and = true;
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if (cell->type.in("$and", "$logic_and") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1)
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if (cell->type.in("$and", "$logic_and") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1 && !cell->getParam("\\A_SIGNED").as_bool())
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detect_const_and = true;
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detect_const_and = true;
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if (cell->type.in("$reduce_or", "$reduce_bool", "$_OR_"))
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if (cell->type.in("$reduce_or", "$reduce_bool", "$_OR_"))
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detect_const_or = true;
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detect_const_or = true;
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if (cell->type.in("$or", "$logic_or") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1)
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if (cell->type.in("$or", "$logic_or") && GetSize(cell->getPort("\\A")) == 1 && GetSize(cell->getPort("\\B")) == 1 && !cell->getParam("\\A_SIGNED").as_bool())
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detect_const_or = true;
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detect_const_or = true;
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if (detect_const_and || detect_const_or)
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if (detect_const_and || detect_const_or)
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