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Get rid of sigBset too

This commit is contained in:
Eddie Hung 2019-09-04 17:22:02 -07:00
parent 91ef4457b0
commit 09c26c55bb
2 changed files with 10 additions and 12 deletions
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4
passes/pmgen/xilinx_dsp.cc
View File

@ -23,10 +23,6 @@
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN PRIVATE_NAMESPACE_BEGIN
template<class T> inline bool includes(const T &lhs, const T &rhs) {
return std::includes(lhs.begin(), lhs.end(), rhs.begin(), rhs.end());
}
#include <set>
#include "passes/pmgen/xilinx_dsp_pm.h" #include "passes/pmgen/xilinx_dsp_pm.h"
void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm) void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)

18
passes/pmgen/xilinx_dsp.pmg
View File

@ -1,24 +1,25 @@
pattern xilinx_dsp pattern xilinx_dsp
state <SigBit> clock state <SigBit> clock
state <std::set<SigBit>> sigBset state <SigSpec> sigA sigB sigC sigM sigP sigPused
state <SigSpec> sigA sigC sigM sigP sigPused
state <IdString> ffMmuxAB postAddAB postAddMuxAB state <IdString> ffMmuxAB postAddAB postAddMuxAB
match dsp match dsp
select dsp->type.in(\DSP48E1) select dsp->type.in(\DSP48E1)
endmatch endmatch
code sigA sigBset code sigA sigB
sigA = port(dsp, \A); sigA = port(dsp, \A);
int i; int i;
for (i = GetSize(sigA)-1; i > 0; i--) for (i = GetSize(sigA)-1; i > 0; i--)
if (sigA[i] != sigA[i-1]) if (sigA[i] != sigA[i-1])
break; break;
sigA.remove(i, GetSize(sigA)-i); sigA.remove(i, GetSize(sigA)-i);
SigSpec B = port(dsp, \B); sigB = port(dsp, \B);
B.remove_const(); for (i = GetSize(sigB)-1; i > 0; i--)
sigBset = B.to_sigbit_set(); if (sigB[i] != sigB[i-1])
break;
sigB.remove(i, GetSize(sigB)-i);
endcode endcode
code sigM code sigM
@ -58,11 +59,12 @@ endcode
match ffB match ffB
if param(dsp, \BREG).as_int() == 0 if param(dsp, \BREG).as_int() == 0
if !sigBset.empty()
select ffB->type.in($dff) select ffB->type.in($dff)
// DSP48E1 does not support clock inversion // DSP48E1 does not support clock inversion
select param(ffB, \CLK_POLARITY).as_bool() select param(ffB, \CLK_POLARITY).as_bool()
filter includes(port(ffB, \Q).to_sigbit_set(), sigBset) filter GetSize(port(ffB, \Q)) >= GetSize(sigB)
slice offset GetSize(port(ffB, \Q))
filter offset+GetSize(sigB) <= GetSize(port(ffB, \Q)) && port(ffB, \Q).extract(offset, GetSize(sigB)) == sigB
optional optional
endmatch endmatch