mirror of https://github.com/YosysHQ/yosys.git
ice40_dsp to accept $__MUL16X16 too
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@ -6,7 +6,7 @@ state <SigSpec> sigA sigB sigY sigS
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state <Cell*> addAB muxAB
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state <Cell*> addAB muxAB
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match mul
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match mul
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select mul->type.in($mul)
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select mul->type.in($mul, $__MUL16X16)
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select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
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select GetSize(mul->getPort(\A)) + GetSize(mul->getPort(\B)) > 10
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select GetSize(mul->getPort(\Y)) > 10
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select GetSize(mul->getPort(\Y)) > 10
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endmatch
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endmatch
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