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tests: zinit on $adff

This commit is contained in:
Eddie Hung 2020-04-13 14:29:44 -07:00
parent 70bca35f9c
commit 091297b9ee
1 changed files with 18 additions and 19 deletions
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37
tests/techmap/zinit.ys
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@ -1,24 +1,23 @@
read_verilog -icells <<EOT read_verilog -icells <<EOT
module top(input C, D, S, R, output [16:0] Q); module top(input C, R, input [1:0] D, (* init = {12{1'b1}} *) output [11:0] Q);
(* init = {17{1'b1}} *)
wire [16:0] Q;
$_DFF_NN0_ dff0 (.C(C), .D(D), .R(R), .Q(Q[0]));
$_DFF_NN1_ dff1 (.C(C), .D(D), .R(R), .Q(Q[1]));
$_DFF_NP0_ dff2 (.C(C), .D(D), .R(R), .Q(Q[2]));
$_DFF_NP1_ dff3 (.C(C), .D(D), .R(R), .Q(Q[3]));
$_DFF_PN0_ dff4 (.C(C), .D(D), .R(R), .Q(Q[4]));
$_DFF_PN1_ dff5 (.C(C), .D(D), .R(R), .Q(Q[5]));
$_DFF_PP0_ dff6 (.C(C), .D(D), .R(R), .Q(Q[6]));
$_DFF_PP1_ dff7 (.C(C), .D(D), .R(R), .Q(Q[7]));
//$_DFFSR_NNN_ dffsr0 (.C(C), .D(D), .S(S), .R(R), .Q(Q[8])); (* init = 1'b1 *)
//$_DFFSR_NNP_ dffsr1 (.C(C), .D(D), .S(S), .R(R), .Q(Q[9])); wire unused;
//$_DFFSR_NPN_ dffsr2 (.C(C), .D(D), .S(S), .R(R), .Q(Q[10]));
//$_DFFSR_NPP_ dffsr3 (.C(C), .D(D), .S(S), .R(R), .Q(Q[11])); $_DFF_NN0_ dff0 (.C(C), .D(D[0]), .R(R), .Q(Q[0]));
//$_DFFSR_PNN_ dffsr4 (.C(C), .D(D), .S(S), .R(R), .Q(Q[12])); $_DFF_NN1_ dff1 (.C(C), .D(D[0]), .R(R), .Q(Q[1]));
//$_DFFSR_PNP_ dffsr5 (.C(C), .D(D), .S(S), .R(R), .Q(Q[13])); $_DFF_NP0_ dff2 (.C(C), .D(D[0]), .R(R), .Q(Q[2]));
//$_DFFSR_PPN_ dffsr6 (.C(C), .D(D), .S(S), .R(R), .Q(Q[14])); $_DFF_NP1_ dff3 (.C(C), .D(D[0]), .R(R), .Q(Q[3]));
//$_DFFSR_PPP_ dffsr7 (.C(C), .D(D), .S(S), .R(R), .Q(Q[15])); $_DFF_PN0_ dff4 (.C(C), .D(D[0]), .R(R), .Q(Q[4]));
$_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
$_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
$_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'd2)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[9:8]));
$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'd1)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[11:10]));
endmodule endmodule
EOT EOT
equiv_opt -map +/simcells.v -multiclock zinit equiv_opt -map +/simcells.v -multiclock zinit
design -load postopt
select -assert-count 1 w:unused a:init %i