riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

verilog: fix leaking ASTNodes

This commit is contained in:
Xiretza 2021-03-16 16:43:03 +01:00 committed by Zachary Snow
parent 9ca5a91724
commit 091295a5a5
2 changed files with 15 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
frontends/ast/simplify.cc
View File

@ -2303,6 +2303,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage,
if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT) if (left_at_zero_ast->type != AST_CONSTANT || right_at_zero_ast->type != AST_CONSTANT)
log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str()); log_file_error(filename, location.first_line, "Unsupported expression on dynamic range select on signal `%s'!\n", str.c_str());
result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1; result_width = abs(int(left_at_zero_ast->integer - right_at_zero_ast->integer)) + 1;
delete left_at_zero_ast;
delete right_at_zero_ast;
} }
bool use_case_method = false; bool use_case_method = false;
@ -3534,6 +3536,8 @@ skip_dynamic_range_lvalue_expansion:;
// convert purely constant arguments into localparams // convert purely constant arguments into localparams
if (child->is_input && child->type == AST_WIRE && arg->type == AST_CONSTANT && node_contains_assignment_to(decl, child)) { if (child->is_input && child->type == AST_WIRE && arg->type == AST_CONSTANT && node_contains_assignment_to(decl, child)) {
wire->type = AST_LOCALPARAM; wire->type = AST_LOCALPARAM;
if (wire->attributes.count(ID::nosync))
delete wire->attributes.at(ID::nosync);
wire->attributes.erase(ID::nosync); wire->attributes.erase(ID::nosync);
wire->children.insert(wire->children.begin(), arg->clone()); wire->children.insert(wire->children.begin(), arg->clone());
// args without a range implicitly have width 1 // args without a range implicitly have width 1
@ -3557,6 +3561,7 @@ skip_dynamic_range_lvalue_expansion:;
} }
// updates the sizing // updates the sizing
while (wire->simplify(true, false, false, 1, -1, false, false)) { } while (wire->simplify(true, false, false, 1, -1, false, false)) { }
delete arg;
continue; continue;
} }
AstNode *wire_id = new AstNode(AST_IDENTIFIER); AstNode *wire_id = new AstNode(AST_IDENTIFIER);

17
frontends/verilog/verilog_parser.y
View File

@ -503,18 +503,19 @@ optional_comma:
module_arg_opt_assignment: module_arg_opt_assignment:
'=' expr { '=' expr {
if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) { if (ast_stack.back()->children.size() > 0 && ast_stack.back()->children.back()->type == AST_WIRE) {
AstNode *wire = new AstNode(AST_IDENTIFIER);
wire->str = ast_stack.back()->children.back()->str;
if (ast_stack.back()->children.back()->is_input) { if (ast_stack.back()->children.back()->is_input) {
AstNode *n = ast_stack.back()->children.back(); AstNode *n = ast_stack.back()->children.back();
if (n->attributes.count(ID::defaultvalue)) if (n->attributes.count(ID::defaultvalue))
delete n->attributes.at(ID::defaultvalue); delete n->attributes.at(ID::defaultvalue);
n->attributes[ID::defaultvalue] = $2; n->attributes[ID::defaultvalue] = $2;
} else } else {
if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic) AstNode *wire = new AstNode(AST_IDENTIFIER);
ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2)))); wire->str = ast_stack.back()->children.back()->str;
else if (ast_stack.back()->children.back()->is_reg || ast_stack.back()->children.back()->is_logic)
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2)); ast_stack.back()->children.push_back(new AstNode(AST_INITIAL, new AstNode(AST_BLOCK, new AstNode(AST_ASSIGN_LE, wire, $2))));
else
ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, wire, $2));
}
} else } else
frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value."); frontend_verilog_yyerror("SystemVerilog interface in module port list cannot have a default value.");
} | } |
@ -1158,6 +1159,8 @@ specify_item:
cell->children.back()->str = "\\DST"; cell->children.back()->str = "\\DST";
delete $1; delete $1;
delete limit;
delete limit2;
}; };
specify_opt_triple: specify_opt_triple: