mirror of https://github.com/YosysHQ/yosys.git
Added opt_share -share_all
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09ef279b60
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@ -38,12 +38,12 @@ struct OptPass : public Pass {
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log("passes in the following order:\n");
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log("\n");
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log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]\n");
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log(" opt_share -nomux\n");
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log(" opt_share [-share_all] -nomux\n");
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log("\n");
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log(" do\n");
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log(" opt_muxtree\n");
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log(" opt_reduce [-fine] [-full]\n");
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log(" opt_share\n");
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log(" opt_share [-share_all]\n");
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log(" opt_rmdff\n");
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log(" opt_clean [-purge]\n");
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log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]\n");
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@ -53,7 +53,7 @@ struct OptPass : public Pass {
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log("\n");
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log(" do\n");
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log(" opt_const [-mux_undef] [-mux_bool] [-undriven] [-fine] [-full] [-keepdc]\n");
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log(" opt_share\n");
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log(" opt_share [-share_all]\n");
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log(" opt_rmdff\n");
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log(" opt_clean [-purge]\n");
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log(" while <changed design in opt_rmdff>\n");
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@ -68,6 +68,7 @@ struct OptPass : public Pass {
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std::string opt_clean_args;
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std::string opt_const_args;
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std::string opt_reduce_args;
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std::string opt_share_args;
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bool fast_mode = false;
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log_header("Executing OPT pass (performing simple optimizations).\n");
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@ -105,6 +106,10 @@ struct OptPass : public Pass {
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opt_const_args += " -keepdc";
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continue;
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}
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if (args[argidx] == "-share_all") {
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opt_share_args += " -share_all";
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continue;
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}
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if (args[argidx] == "-fast") {
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fast_mode = true;
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continue;
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@ -117,7 +122,7 @@ struct OptPass : public Pass {
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{
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while (1) {
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Pass::call(design, "opt_const" + opt_const_args);
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Pass::call(design, "opt_share");
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Pass::call(design, "opt_share" + opt_share_args);
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design->scratchpad_unset("opt.did_something");
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Pass::call(design, "opt_rmdff");
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if (design->scratchpad_get_bool("opt.did_something") == false)
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@ -130,12 +135,12 @@ struct OptPass : public Pass {
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else
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{
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Pass::call(design, "opt_const" + opt_const_args);
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Pass::call(design, "opt_share -nomux");
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Pass::call(design, "opt_share -nomux" + opt_share_args);
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while (1) {
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design->scratchpad_unset("opt.did_something");
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Pass::call(design, "opt_muxtree");
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Pass::call(design, "opt_reduce" + opt_reduce_args);
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Pass::call(design, "opt_share");
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Pass::call(design, "opt_share" + opt_share_args);
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Pass::call(design, "opt_rmdff");
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Pass::call(design, "opt_clean" + opt_clean_args);
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Pass::call(design, "opt_const" + opt_const_args);
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@ -37,6 +37,7 @@ struct OptShareWorker
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RTLIL::Module *module;
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SigMap assign_map;
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SigMap dff_init_map;
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bool mode_share_all;
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CellTypes ct;
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int total_count;
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@ -93,7 +94,7 @@ struct OptShareWorker
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}
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for (auto &it : *conn) {
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if (ct.cell_output(cell->type, it.first))
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if (cell->output(it.first))
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continue;
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RTLIL::SigSpec sig = it.second;
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assign_map.apply(sig);
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@ -137,14 +138,14 @@ struct OptShareWorker
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dict<RTLIL::IdString, RTLIL::SigSpec> conn2 = cell2->connections();
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for (auto &it : conn1) {
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if (ct.cell_output(cell1->type, it.first))
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if (cell1->output(it.first))
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it.second = RTLIL::SigSpec();
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else
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assign_map.apply(it.second);
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}
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for (auto &it : conn2) {
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if (ct.cell_output(cell2->type, it.first))
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if (cell2->output(it.first))
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it.second = RTLIL::SigSpec();
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else
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assign_map.apply(it.second);
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@ -197,7 +198,7 @@ struct OptShareWorker
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if (cell1->type != cell2->type)
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return cell1->type < cell2->type;
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if (!ct.cell_known(cell1->type))
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if ((!mode_share_all && !ct.cell_known(cell1->type)) || !cell1->known())
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return cell1 < cell2;
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if (cell1->has_keep_attr() || cell2->has_keep_attr())
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@ -218,8 +219,8 @@ struct OptShareWorker
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}
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};
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OptShareWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux) :
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design(design), module(module), assign_map(module)
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OptShareWorker(RTLIL::Design *design, RTLIL::Module *module, bool mode_nomux, bool mode_share_all) :
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design(design), module(module), assign_map(module), mode_share_all(mode_share_all)
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{
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total_count = 0;
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ct.setup_internals();
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@ -249,7 +250,9 @@ struct OptShareWorker
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std::vector<RTLIL::Cell*> cells;
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cells.reserve(module->cells_.size());
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for (auto &it : module->cells_) {
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if (ct.cell_known(it.second->type) && design->selected(module, it.second))
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if (!design->selected(module, it.second))
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continue;
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if (ct.cell_known(it.second->type) || (mode_share_all && it.second->known()))
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cells.push_back(it.second);
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}
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@ -261,7 +264,7 @@ struct OptShareWorker
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did_something = true;
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log(" Cell `%s' is identical to cell `%s'.\n", cell->name.c_str(), sharemap[cell]->name.c_str());
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for (auto &it : cell->connections()) {
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if (ct.cell_output(cell->type, it.first)) {
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if (cell->output(it.first)) {
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RTLIL::SigSpec other_sig = sharemap[cell]->getPort(it.first);
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log(" Redirecting output %s: %s = %s\n", it.first.c_str(),
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log_signal(it.second), log_signal(other_sig));
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@ -287,7 +290,7 @@ struct OptSharePass : public Pass {
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_share [-nomux] [selection]\n");
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log(" opt_share [options] [selection]\n");
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log("\n");
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log("This pass identifies cells with identical type and input signals. Such cells\n");
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log("are then merged to one cell.\n");
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@ -295,12 +298,16 @@ struct OptSharePass : public Pass {
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log(" -nomux\n");
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log(" Do not merge MUX cells.\n");
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log("\n");
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log(" -share_all\n");
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log(" Operate on all cell types, not just built-in types.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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log_header("Executing OPT_SHARE pass (detect identical cells).\n");
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bool mode_nomux = false;
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bool mode_share_all = false;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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@ -309,13 +316,17 @@ struct OptSharePass : public Pass {
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mode_nomux = true;
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continue;
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}
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if (arg == "-share_all") {
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mode_share_all = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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int total_count = 0;
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for (auto module : design->selected_modules()) {
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OptShareWorker worker(design, module, mode_nomux);
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OptShareWorker worker(design, module, mode_nomux, mode_share_all);
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total_count += worker.total_count;
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}
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