mirror of https://github.com/YosysHQ/yosys.git
Implemented simplemap support for "techmap -extern"
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@ -326,8 +326,40 @@ struct TechmapWorker
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{
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if (extern_mode)
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{
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log("WARNING: Mapping simplemap cell %s.%s (%s) in -extern mode is not supported yet.\n", log_id(module), log_id(cell), log_id(cell->type));
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break;
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std::string m_name = stringf("$extern:simplemap:%s", log_id(cell->type));
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for (auto &c : cell->parameters)
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m_name += stringf(":%s=%s", log_id(c.first), log_signal(c.second));
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RTLIL::Module *simplemap_module = design->module(m_name);
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if (simplemap_module == nullptr)
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{
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simplemap_module = design->addModule(m_name);
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RTLIL::Cell *simplemap_cell = simplemap_module->addCell(cell->type, cell);
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int port_counter = 1;
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for (auto &c : simplemap_cell->connections_) {
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RTLIL::Wire *w = simplemap_module->addWire(c.first, SIZE(c.second));
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if (w->name == "\\Y" || w->name == "\\Q")
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w->port_output = true;
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else
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w->port_input = true;
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w->port_id = port_counter++;
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c.second = w;
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}
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simplemap_module->check();
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log("Creating %s with simplemap.\n", log_id(simplemap_module));
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if (simplemap_mappers.count(simplemap_cell->type) == 0)
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log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(simplemap_cell->type));
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simplemap_mappers.at(simplemap_cell->type)(simplemap_module, simplemap_cell);
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simplemap_module->remove(simplemap_cell);
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}
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cell->type = m_name;
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cell->parameters.clear();
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}
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else
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{
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@ -337,10 +369,11 @@ struct TechmapWorker
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simplemap_mappers.at(cell->type)(module, cell);
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module->remove(cell);
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cell = NULL;
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did_something = true;
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mapped_cell = true;
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break;
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}
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did_something = true;
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mapped_cell = true;
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break;
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}
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for (auto conn : cell->connections()) {
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@ -538,6 +571,8 @@ struct TechmapWorker
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port_conn.second.append_bit(it.second);
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}
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tpl->connect(port_conn);
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tpl->check();
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}
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Pass::call_on_module(map, tpl, cmd_string);
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