riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

fixup! abstract: -state MVP

This commit is contained in:
Emil J. Tywoniak 2025-01-30 17:52:55 +01:00
parent 17b8b7352c
commit 083759676a
2 changed files with 40 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
passes/cmds/abstract.cc
View File

@ -14,19 +14,23 @@ bool abstract_state(Module* mod, Cell* cell, Wire* enable, bool enable_pol) {
// Doesn't matter if there was an enable signal already // Doesn't matter if there was an enable signal already
// we discard it and mux with symbolic value // we discard it and mux with symbolic value
ff.has_ce = false; ff.has_ce = false;
ff.emit(); Wire* inp = cell->getPort(ID::D).as_wire();
cell = ff.emit();
auto inp = cell->getPort(ID::D); Wire* abstracted = mod->addWire(NEW_ID, inp->width);
Wire* abstracted = mod->addWire(NEW_ID, inp.size());
SigSpec mux_a, mux_b; SigSpec mux_a, mux_b;
if (enable_pol) { if (enable_pol) {
mux_a = inp; mux_a = inp;
mux_b = mod->Anyseq(NEW_ID, inp.size()); mux_b = mod->Anyseq(NEW_ID, inp->width);
} else { } else {
mux_a = mod->Anyseq(NEW_ID, inp.size()); mux_a = mod->Anyseq(NEW_ID, inp->width);
mux_b = inp; mux_b = inp;
} }
(void)mod->addMux(NEW_ID, mux_a, mux_b, enable, abstracted); (void)mod->addMux(NEW_ID,
mux_a,
mux_b,
enable,
abstracted);
cell->setPort(ID::D, SigSpec(abstracted)); cell->setPort(ID::D, SigSpec(abstracted));
return true; return true;
} }
@ -87,6 +91,8 @@ struct AbstractPass : public Pass {
for (auto mod : design->selected_modules()) { for (auto mod : design->selected_modules()) {
log("module %s\n", mod->name.c_str()); log("module %s\n", mod->name.c_str());
Wire *enable_wire = mod->wire("\\" + enable_name); Wire *enable_wire = mod->wire("\\" + enable_name);
if (!enable_wire)
log_cmd_error("Enable wire %s not found in module %s\n", enable_name.c_str(), mod->name.c_str());
if (mode == State) { if (mode == State) {
for (auto cell : mod->selected_cells()) { for (auto cell : mod->selected_cells()) {
log("cell %s\n", cell->name.c_str()); log("cell %s\n", cell->name.c_str());
@ -102,7 +108,7 @@ struct AbstractPass : public Pass {
} else { } else {
log_cmd_error("No mode selected, see help message\n"); log_cmd_error("No mode selected, see help message\n");
} }
log("Abstracted %d cells\n", changed_cells); log("Abstracted %d cell(s).\n", changed_cells);
} }
} AbstractPass; } AbstractPass;

27
tests/various/abstract.ys
View File

@ -10,5 +10,32 @@ endmodule
EOT EOT
proc proc
# dump
abstract -state -enablen magic abstract -state -enablen magic
check
# dump
design -reset
read_verilog <<EOT
module half_clock_en (CLK, E, Q);
input CLK;
input E;
output reg Q;
reg magic;
always @(posedge CLK)
if (E)
Q <= ~Q;
endmodule
EOT
proc
opt_expr
opt_dff
# show # show
# dump
abstract -state -enablen magic
check
# opt_clean
# show