mirror of https://github.com/YosysHQ/yosys.git
fixup! abstract: -state MVP
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@ -14,19 +14,23 @@ bool abstract_state(Module* mod, Cell* cell, Wire* enable, bool enable_pol) {
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// Doesn't matter if there was an enable signal already
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// we discard it and mux with symbolic value
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ff.has_ce = false;
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ff.emit();
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Wire* inp = cell->getPort(ID::D).as_wire();
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cell = ff.emit();
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auto inp = cell->getPort(ID::D);
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Wire* abstracted = mod->addWire(NEW_ID, inp.size());
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Wire* abstracted = mod->addWire(NEW_ID, inp->width);
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SigSpec mux_a, mux_b;
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if (enable_pol) {
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mux_a = inp;
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mux_b = mod->Anyseq(NEW_ID, inp.size());
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mux_b = mod->Anyseq(NEW_ID, inp->width);
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} else {
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mux_a = mod->Anyseq(NEW_ID, inp.size());
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mux_a = mod->Anyseq(NEW_ID, inp->width);
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mux_b = inp;
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}
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(void)mod->addMux(NEW_ID, mux_a, mux_b, enable, abstracted);
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(void)mod->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable,
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abstracted);
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cell->setPort(ID::D, SigSpec(abstracted));
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return true;
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}
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@ -87,6 +91,8 @@ struct AbstractPass : public Pass {
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for (auto mod : design->selected_modules()) {
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log("module %s\n", mod->name.c_str());
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Wire *enable_wire = mod->wire("\\" + enable_name);
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if (!enable_wire)
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log_cmd_error("Enable wire %s not found in module %s\n", enable_name.c_str(), mod->name.c_str());
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if (mode == State) {
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for (auto cell : mod->selected_cells()) {
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log("cell %s\n", cell->name.c_str());
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@ -102,7 +108,7 @@ struct AbstractPass : public Pass {
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} else {
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log_cmd_error("No mode selected, see help message\n");
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}
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log("Abstracted %d cells\n", changed_cells);
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log("Abstracted %d cell(s).\n", changed_cells);
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}
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} AbstractPass;
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@ -10,5 +10,32 @@ endmodule
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EOT
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proc
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# dump
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abstract -state -enablen magic
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check
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# dump
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design -reset
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read_verilog <<EOT
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module half_clock_en (CLK, E, Q);
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input CLK;
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input E;
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output reg Q;
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reg magic;
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always @(posedge CLK)
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if (E)
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Q <= ~Q;
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endmodule
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EOT
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proc
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opt_expr
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opt_dff
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# show
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# dump
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abstract -state -enablen magic
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check
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# opt_clean
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# show
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