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Add "expose -input" 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-03-12 13:52:52 +01:00
parent 83ffb23739
commit 08225f49a4
1 changed files with 44 additions and 9 deletions
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53
passes/sat/expose.cc
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@ -236,6 +236,10 @@ struct ExposePass : public Pass {
log(" when exposing a wire, create an input/output pair and cut the internal\n"); log(" when exposing a wire, create an input/output pair and cut the internal\n");
log(" signal path at that wire.\n"); log(" signal path at that wire.\n");
log("\n"); log("\n");
log(" -input\n");
log(" when exposing a wire, create an input port and disconnect the internal\n");
log(" driver.\n");
log("\n");
log(" -shared\n"); log(" -shared\n");
log(" only expose those signals that are shared among the selected modules.\n"); log(" only expose those signals that are shared among the selected modules.\n");
log(" this is useful for preparing modules for equivalence checking.\n"); log(" this is useful for preparing modules for equivalence checking.\n");
@ -259,6 +263,7 @@ struct ExposePass : public Pass {
bool flag_evert = false; bool flag_evert = false;
bool flag_dff = false; bool flag_dff = false;
bool flag_cut = false; bool flag_cut = false;
bool flag_input = false;
bool flag_evert_dff = false; bool flag_evert_dff = false;
std::string sep = "."; std::string sep = ".";
@ -279,10 +284,14 @@ struct ExposePass : public Pass {
flag_dff = true; flag_dff = true;
continue; continue;
} }
if (args[argidx] == "-cut") { if (args[argidx] == "-cut" && !flag_input) {
flag_cut = true; flag_cut = true;
continue; continue;
} }
if (args[argidx] == "-input" && !flag_cut) {
flag_input = true;
continue;
}
if (args[argidx] == "-evert-dff") { if (args[argidx] == "-evert-dff") {
flag_evert_dff = true; flag_evert_dff = true;
continue; continue;
@ -464,16 +473,42 @@ struct ExposePass : public Pass {
continue; continue;
} }
if (!it.second->port_output) { if (flag_input)
it.second->port_output = true; {
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name)); if (!it.second->port_input) {
it.second->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
RTLIL::Wire *w = module->addWire(NEW_ID, GetSize(it.second));
out_to_in_map.add(it.second, w);
}
}
else
{
if (!it.second->port_output) {
it.second->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name));
}
if (flag_cut) {
RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width);
in_wire->port_input = true;
out_to_in_map.add(sigmap(it.second), in_wire);
}
}
}
if (flag_input)
{
for (auto &it : module->cells_) {
if (!ct.cell_known(it.second->type))
continue;
for (auto &conn : it.second->connections_)
if (ct.cell_output(it.second->type, conn.first))
conn.second = out_to_in_map(sigmap(conn.second));
} }
if (flag_cut) { for (auto &conn : module->connections_)
RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width); conn.first = out_to_in_map(sigmap(conn.first));
in_wire->port_input = true;
out_to_in_map.add(sigmap(it.second), in_wire);
}
} }
if (flag_cut) if (flag_cut)