mirror of https://github.com/YosysHQ/yosys.git
Do not double count LUT1s
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fdfc18be91
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0800846e73
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@ -670,7 +670,6 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
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RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
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RTLIL::SigBit(module->wires_[remap_name(y_bit.wire->name)], y_bit.offset),
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driver_lut);
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driver_lut);
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}
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}
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cell_stats["$lut"]++;
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}
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}
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else {
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else {
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cell = module->addCell(remap_name(c->name), "$_NOT_");
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cell = module->addCell(remap_name(c->name), "$_NOT_");
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