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rtlil: handle all-zeros case in Const::compress
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@ -293,13 +293,15 @@ void RTLIL::Const::compress(bool is_signed)
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size_t idx = bits.size();
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while (idx > 0 && bits[idx -1] == leading_bit) {
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--idx;
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idx--;
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}
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// signed needs one leading bit
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if (is_signed && idx < bits.size()) {
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++idx;
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idx++;
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}
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// must be at least one bit
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idx = (idx == 0) ? 1 : idx;
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bits.erase(bits.begin() + idx, bits.end());
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}
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