mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4467 from povik/fix-add-shiftx
rtlil: Fix `addShiftx` for signed shifts
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commit
07daf61ae6
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@ -2517,7 +2517,6 @@ DEF_METHOD(Or, max(sig_a.size(), sig_b.size()), ID($or))
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DEF_METHOD(Xor, max(sig_a.size(), sig_b.size()), ID($xor))
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DEF_METHOD(Xnor, max(sig_a.size(), sig_b.size()), ID($xnor))
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DEF_METHOD(Shift, sig_a.size(), ID($shift))
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DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
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DEF_METHOD(Lt, 1, ID($lt))
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DEF_METHOD(Le, 1, ID($le))
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DEF_METHOD(Eq, 1, ID($eq))
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@ -2562,6 +2561,28 @@ DEF_METHOD(Sshl, sig_a.size(), ID($sshl))
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DEF_METHOD(Sshr, sig_a.size(), ID($sshr))
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#undef DEF_METHOD
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#define DEF_METHOD(_func, _y_size, _type) \
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RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \
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RTLIL::Cell *cell = addCell(name, _type); \
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cell->parameters[ID::A_SIGNED] = false; \
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cell->parameters[ID::B_SIGNED] = is_signed; \
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cell->parameters[ID::A_WIDTH] = sig_a.size(); \
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cell->parameters[ID::B_WIDTH] = sig_b.size(); \
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cell->parameters[ID::Y_WIDTH] = sig_y.size(); \
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cell->setPort(ID::A, sig_a); \
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cell->setPort(ID::B, sig_b); \
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cell->setPort(ID::Y, sig_y); \
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cell->set_src_attribute(src); \
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return cell; \
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} \
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RTLIL::SigSpec RTLIL::Module::_func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, bool is_signed, const std::string &src) { \
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RTLIL::SigSpec sig_y = addWire(NEW_ID, _y_size); \
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add ## _func(name, sig_a, sig_b, sig_y, is_signed, src); \
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return sig_y; \
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}
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DEF_METHOD(Shiftx, sig_a.size(), ID($shiftx))
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#undef DEF_METHOD
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#define DEF_METHOD(_func, _type, _pmux) \
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RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_b, const RTLIL::SigSpec &sig_s, const RTLIL::SigSpec &sig_y, const std::string &src) { \
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RTLIL::Cell *cell = addCell(name, _type); \
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