mirror of https://github.com/YosysHQ/yosys.git
Clean up `passes/cmds/scatter.cc`.
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8d3f6d0d79
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0787af947f
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@ -46,22 +46,19 @@ struct ScatterPass : public Pass {
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CellTypes ct(design);
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CellTypes ct(design);
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extra_args(args, 1, design);
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extra_args(args, 1, design);
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for (auto &mod_it : design->modules_)
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for (auto module : design->selected_modules())
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{
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{
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if (!design->selected(mod_it.second))
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for (auto cell : module->cells())
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continue;
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for (auto &p : cell->connections_)
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for (auto &c : mod_it.second->cells_)
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for (auto &p : c.second->connections_)
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{
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{
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RTLIL::Wire *wire = mod_it.second->addWire(NEW_ID, p.second.size());
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RTLIL::Wire *wire = module->addWire(NEW_ID, p.second.size());
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if (ct.cell_output(c.second->type, p.first)) {
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if (ct.cell_output(cell->type, p.first)) {
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RTLIL::SigSig sigsig(p.second, wire);
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RTLIL::SigSig sigsig(p.second, wire);
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mod_it.second->connect(sigsig);
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module->connect(sigsig);
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} else {
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} else {
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RTLIL::SigSig sigsig(wire, p.second);
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RTLIL::SigSig sigsig(wire, p.second);
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mod_it.second->connect(sigsig);
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module->connect(sigsig);
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}
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}
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p.second = wire;
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p.second = wire;
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