riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Bugfix in wreduce

This commit is contained in:
Clifford Wolf 2015-02-16 09:08:00 +01:00
parent 162432a722
commit 0748ef638d
1 changed files with 14 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
passes/opt/wreduce.cc
View File

@ -281,6 +281,10 @@ struct WreduceWorker
work_queue_cells.insert(port.cell); work_queue_cells.insert(port.cell);
} }
pool<SigSpec> complete_wires;
for (auto w : module->wires())
complete_wires.insert(mi.sigmap(w));
for (auto w : module->selected_wires()) for (auto w : module->selected_wires())
{ {
int unused_top_bits = 0; int unused_top_bits = 0;
@ -296,13 +300,16 @@ struct WreduceWorker
unused_top_bits++; unused_top_bits++;
} }
if (0 < unused_top_bits && unused_top_bits < GetSize(w)) { if (unused_top_bits == 0 || unused_top_bits == GetSize(w))
log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w)); continue;
Wire *nw = module->addWire(NEW_ID, w);
nw->width = GetSize(w) - unused_top_bits; if (complete_wires[mi.sigmap(w).extract(0, GetSize(w) - unused_top_bits)])
module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); continue;
module->swap_names(w, nw);
} log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module), log_id(w));
Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits);
module->connect(nw, SigSpec(w).extract(0, GetSize(nw)));
module->swap_names(w, nw);
} }
} }
}; };