mirror of https://github.com/YosysHQ/yosys.git
Working
This commit is contained in:
Eddie Hung
parent
e7ef7fa443
commit
06f8f2654a
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@ -26,7 +26,9 @@ PRIVATE_NAMESPACE_BEGIN
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struct ShregmapTech
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{
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virtual ~ShregmapTech() { }
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virtual bool analyze(vector<int> &taps) = 0;
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virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
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virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
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virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
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virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
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};
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@ -54,7 +56,7 @@ struct ShregmapOptions
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struct ShregmapTechGreenpak4 : ShregmapTech
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{
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bool analyze(vector<int> &taps)
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bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/)
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{
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if (GetSize(taps) > 2 && taps[0] == 0 && taps[2] < 17) {
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taps.clear();
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@ -91,6 +93,120 @@ struct ShregmapTechGreenpak4 : ShregmapTech
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}
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};
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struct ShregmapTechXilinx7 : ShregmapTech
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{
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dict<SigBit, Cell*> sigbit_to_shiftx;
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const ShregmapOptions &opts;
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ShregmapTechXilinx7(const ShregmapOptions &opts) : opts(opts) {}
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virtual void init(const Module* module, const SigMap &sigmap) override
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{
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for (auto i : module->cells_) {
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auto cell = i.second;
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if (cell->type != "$shiftx") continue;
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if (cell->getParam("\\Y_WIDTH") != 1) continue;
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for (auto bit : sigmap(cell->getPort("\\A")))
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sigbit_to_shiftx[bit] = cell;
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}
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}
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virtual void non_chain_user(const SigBit &bit, const Cell *cell, IdString port) override
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{
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auto it = sigbit_to_shiftx.find(bit);
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if (it == sigbit_to_shiftx.end())
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return;
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if (cell->type == "$shiftx" && port == "\\A")
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return;
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it->second = nullptr;
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}
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virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) override
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{
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if (GetSize(taps) == 1)
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return taps[0] >= opts.minlen-1;
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if (taps.back() < opts.minlen-1)
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return false;
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Cell *shiftx = nullptr;
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int offset = 0;
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for (int i = 0; i < GetSize(taps); ++i) {
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// Check taps are sequential
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if (i != taps[i])
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return false;
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// Check taps are not connected to a shift register,
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// or sequential to the same shift register
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auto it = sigbit_to_shiftx.find(qbits[i]);
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if (i == 0) {
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if (it != sigbit_to_shiftx.end()) {
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shiftx = it->second;
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// NULL indicates there are non-shiftx users
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if (shiftx == nullptr)
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return false;
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offset = qbits[i].offset;
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}
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}
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else {
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if (it == sigbit_to_shiftx.end()) {
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if (shiftx != nullptr)
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return false;
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}
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else {
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if (shiftx != it->second)
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return false;
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if (qbits[i].offset != offset + i)
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return false;
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}
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}
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}
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return true;
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}
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virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override
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{
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const auto &tap = *taps.begin();
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auto bit = tap.second;
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auto it = sigbit_to_shiftx.find(bit);
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if (it == sigbit_to_shiftx.end())
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return true;
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Cell* shiftx = it->second;
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auto module = cell->module;
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auto cell_q = cell->getPort("\\Q").as_bit();
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auto shiftx_a = shiftx->getPort("\\A").bits();
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int offset = 0;
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for (auto bit : shiftx_a) {
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if (bit == cell_q)
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break;
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++offset;
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}
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offset -= taps.size() - 1;
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log_assert(offset >= 0);
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for (size_t i = offset; i < offset + taps.size(); ++i)
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shiftx_a[i] = cell_q;
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// FIXME: Hack to ensure that $shiftx gets optimised away
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// Without this, Yosys will refuse to optimise away a $shiftx
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// where \\A 's width is not perfectly \\B_WIDTH ** 2
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auto shiftx_bwidth = shiftx->getParam("\\B_WIDTH").as_int();
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shiftx_a.resize(1 << shiftx_bwidth, shiftx_a.back());
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shiftx->setPort("\\A", shiftx_a);
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shiftx->setParam("\\A_WIDTH", shiftx_a.size());
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auto length = module->addWire(NEW_ID, ceil(log2(taps.size())));
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module->addSub(NEW_ID, shiftx->getPort("\\B"), RTLIL::Const(offset, ceil(log2(offset))), length);
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cell->setPort("\\L", length);
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return true;
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}
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};
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struct ShregmapWorker
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{
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Module *module;
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@ -152,8 +268,10 @@ struct ShregmapWorker
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for (auto conn : cell->connections())
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if (cell->input(conn.first))
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for (auto bit : sigmap(conn.second))
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for (auto bit : sigmap(conn.second)) {
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sigbit_with_non_chain_users.insert(bit);
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if (opts.tech) opts.tech->non_chain_user(bit, cell, conn.first);
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}
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}
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}
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@ -193,7 +311,7 @@ struct ShregmapWorker
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continue;
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}
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start_cell:
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start_cell:
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chain_start_cells.insert(it.second);
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}
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}
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@ -258,7 +376,7 @@ struct ShregmapWorker
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if (taps.empty() || taps.back() < depth-1)
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taps.push_back(depth-1);
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if (opts.tech->analyze(taps))
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if (opts.tech->analyze(taps, qbits))
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break;
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taps.pop_back();
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@ -336,6 +454,8 @@ struct ShregmapWorker
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first_cell->type = shreg_cell_type_str;
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first_cell->setPort(q_port, last_cell->getPort(q_port));
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if (!first_cell->hasPort("\\L"))
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first_cell->setPort("\\L", depth-1);
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first_cell->setParam("\\DEPTH", depth);
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if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict))
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@ -377,6 +497,9 @@ struct ShregmapWorker
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ShregmapWorker(Module *module, const ShregmapOptions &opts) :
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module(module), sigmap(module), opts(opts), dff_count(0), shreg_count(0)
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{
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if (opts.tech)
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opts.tech->init(module, sigmap);
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make_sigbit_chain_next_prev();
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find_chain_start_cells();
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@ -501,6 +624,12 @@ struct ShregmapPass : public Pass {
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clkpol = "pos";
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opts.zinit = true;
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opts.tech = new ShregmapTechGreenpak4;
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}
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else if (tech == "xilinx") {
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opts.init = true;
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opts.params = true;
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enpol = "any_or_none";
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opts.tech = new ShregmapTechXilinx7(opts);
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} else {
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argidx--;
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break;
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@ -17,7 +17,7 @@
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*
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*/
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module \$__SHREG_ (input C, input D, input E, output Q);
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module \$__SHREG_ (input C, input D, input [31:0] L, input E, output Q);
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parameter DEPTH = 0;
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parameter [DEPTH-1:0] INIT = 0;
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parameter CLKPOL = 1;
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@ -36,6 +36,9 @@ module \$__SHREG_ (input C, input D, input E, output Q);
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endfunction
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localparam [DEPTH-1:0] INIT_R = brev(INIT);
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parameter _TECHMAP_CONSTMSK_L_ = 0;
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parameter _TECHMAP_CONSTVAL_L_ = 0;
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generate
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if (ENPOL == 0)
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assign CE = ~E;
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@ -44,60 +47,86 @@ module \$__SHREG_ (input C, input D, input E, output Q);
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else
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assign CE = 1'b1;
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if (DEPTH == 1) begin
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wire _TECHMAP_FAIL_ = ~&_TECHMAP_CONSTMSK_L_ || _TECHMAP_CONSTVAL_L_ != 0;
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if (CLKPOL)
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FDRE #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
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else
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FDRE_1 #(.INIT(INIT_R)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .CE(CE), .R(1'b0));
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end else
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if (DEPTH <= 16) begin
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localparam [3:0] A = DEPTH - 1;
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SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(A[0]), .A1(A[1]), .A2(A[2]), .A3(A[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
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SRL16E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A0(L[0]), .A1(L[1]), .A2(L[2]), .A3(L[3]), .CE(CE), .CLK(C), .D(D), .Q(Q));
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end else
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if (DEPTH > 17 && DEPTH <= 32) begin
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SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(DEPTH-1), .CE(CE), .CLK(C), .D(D), .Q(Q));
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SRLC32E #(.INIT(INIT_R), .IS_CLK_INVERTED(~CLKPOL[0])) _TECHMAP_REPLACE_ (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(Q));
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end else
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if (DEPTH > 33 && DEPTH <= 64) begin
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wire T0, T1, T2;
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localparam [5:0] A = DEPTH-1;
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(A[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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\$__SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .E(E), .Q(T2));
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MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(A[5]));
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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\$__SHREG_ #(.DEPTH(DEPTH-32), .INIT(INIT[DEPTH-32-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T1), .L(L), .E(E), .Q(T2));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T2;
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else
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MUXF7 fpga_mux_0 (.O(Q), .I0(T0), .I1(T2), .S(L[5]));
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end else
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if (DEPTH > 65 && DEPTH <= 96) begin
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localparam [6:0] A = DEPTH-1;
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wire T0, T1, T2, T3, T4, T5, T6;
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(A[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(A[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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\$__SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .E(E), .Q(T4));
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MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(A[5]));
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MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(A[5]));
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MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(A[6]));
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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\$__SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T4;
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else begin
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MUXF7 fpga_mux_0 (.O(T5), .I0(T0), .I1(T2), .S(L[5]));
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MUXF7 fpga_mux_1 (.O(T6), .I0(T4), .I1(1'b0 /* unused */), .S(L[5]));
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MUXF8 fpga_mux_2 (.O(Q), .I0(T5), .I1(T6), .S(L[6]));
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end
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end else
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if (DEPTH > 97 && DEPTH <= 128) begin
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localparam [6:0] A = DEPTH-1;
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wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(A[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(A[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(A[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
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\$__SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .E(E), .Q(T6));
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MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(A[5]));
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MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(A[5]));
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MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(A[6]));
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SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
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SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
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SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
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\$__SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
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if (&_TECHMAP_CONSTMSK_L_)
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assign Q = T6;
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else begin
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MUXF7 fpga_mux_0 (.O(T7), .I0(T0), .I1(T2), .S(L[5]));
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MUXF7 fpga_mux_1 (.O(T8), .I0(T4), .I1(T6), .S(L[5]));
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MUXF8 fpga_mux_2 (.O(Q), .I0(T7), .I1(T8), .S(L[6]));
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end
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else if (DEPTH <= 129) begin
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end
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else if (DEPTH < 129 || (DEPTH <= 129 && &_TECHMAP_CONSTMSK_L_)) begin
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// Handle cases where depth is just 1 over a convenient value,
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// in which case use the flop
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if (&_TECHMAP_CONSTMSK_L_) begin
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// For constant length, use the flop
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wire T0;
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\$__SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .E(E), .Q(T0));
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\$__SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .E(E), .Q(Q));
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end else
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begin
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\$__SHREG_ #(.DEPTH(DEPTH-1), .INIT(INIT[DEPTH-1:1]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(DEPTH-1-1), .E(E), .Q(T0));
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\$__SHREG_ #(.DEPTH(1), .INIT(INIT[0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(0), .E(E), .Q(Q));
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end
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else begin
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// For variable length, bump up to the next length
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// because we can't access Q31
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\$__SHREG_ #(.DEPTH(DEPTH+1), .INIT(INIT), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) _TECHMAP_REPLACE_ (.C(C), .D(D), .L(L), .E(E), .Q(Q));
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end
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end
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else begin
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if (&_TECHMAP_CONSTMSK_L_) begin
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// UG474 (v1.8, p34) states that:
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// "There are no direct connections between slices to form longer shift
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// registers, nor is the MC31 output at LUT B/C/D available."
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wire T0;
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\$__SHREG_ #(.DEPTH(128), .INIT(INIT[DEPTH-1:DEPTH-128]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .E(E), .Q(T0));
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\$__SHREG_ #(.DEPTH(DEPTH-128), .INIT(INIT[DEPTH-128-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .E(E), .Q(Q));
|
||||
\$__SHREG_ #(.DEPTH(128), .INIT(INIT[DEPTH-1:DEPTH-128]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_0 (.C(C), .D(D), .L(127), .E(E), .Q(T0));
|
||||
\$__SHREG_ #(.DEPTH(DEPTH-128), .INIT(INIT[DEPTH-128-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_1 (.C(C), .D(T0), .L(DEPTH-1-128), .E(E), .Q(Q));
|
||||
end
|
||||
else begin
|
||||
// No way to create variable length shift registers >128 bits as Q31
|
||||
// cannot be output to the fabric...
|
||||
wire [DEPTH-1:-1] c;
|
||||
genvar i;
|
||||
for (i = 0; i < DEPTH; i=i+1)
|
||||
\$__SHREG_ #(.DEPTH(1), .INIT(INIT_R[i]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl (.C(C), .D(c[i-1]), .L(0), .E(E), .Q(c[i]));
|
||||
assign { c[-1], Q } = { D, c[L] };
|
||||
end
|
||||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -110,9 +110,8 @@ struct SynthXilinxPass : public Pass
|
|||
log(" dffsr2dff\n");
|
||||
log(" dff2dffe\n");
|
||||
log(" opt -full\n");
|
||||
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v\n");
|
||||
log(" shregmap -init -params -enpol any_or_none\n");
|
||||
log(" techmap -map +/xilinx/ff_map.v\n");
|
||||
log(" shregmap -tech xilinx\n");
|
||||
log(" techmap -map +/techmap.v -map +/xilinx/arith_map.v +/xilinx/ff_map.v\n");
|
||||
log(" opt -fast\n");
|
||||
log("\n");
|
||||
log(" map_luts:\n");
|
||||
|
|
@ -256,14 +255,17 @@ struct SynthXilinxPass : public Pass
|
|||
Pass::call(design, "dff2dffe");
|
||||
Pass::call(design, "opt -full");
|
||||
|
||||
Pass::call(design, "simplemap t:$dff*");
|
||||
Pass::call(design, "shregmap -tech xilinx");
|
||||
Pass::call(design, "techmap -map +/xilinx/cells_map.v t:$__SHREG_");
|
||||
Pass::call(design, "opt -fast");
|
||||
|
||||
if (vpr) {
|
||||
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
|
||||
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v -D _EXPLICIT_CARRY");
|
||||
} else {
|
||||
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v");
|
||||
Pass::call(design, "techmap -map +/techmap.v -map +/xilinx/arith_map.v -map +/xilinx/ff_map.v");
|
||||
}
|
||||
|
||||
Pass::call(design, "shregmap -init -params -enpol any_or_none");
|
||||
Pass::call(design, "techmap -map +/xilinx/ff_map.v");
|
||||
Pass::call(design, "opt -fast");
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue