mirror of https://github.com/YosysHQ/yosys.git
Fix wrong results when opt_share called before opt_clean
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6a796accc0
commit
067b44938c
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@ -177,14 +177,12 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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auto op = p.op;
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auto op = p.op;
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RTLIL::IdString muxed_port_name = "\\A";
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RTLIL::IdString muxed_port_name = "\\A";
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if (op->getPort("\\A") == operand.sig) {
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if (decode_port(op, "\\A", &assign_map) == operand)
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muxed_port_name = "\\B";
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muxed_port_name = "\\B";
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}
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auto operand = decode_port(op, muxed_port_name, &assign_map);
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auto operand = decode_port(op, muxed_port_name, &assign_map);
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if (operand.sig.size() > max_width) {
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if (operand.sig.size() > max_width)
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max_width = operand.sig.size();
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max_width = operand.sig.size();
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}
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muxed_operands.push_back(operand);
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muxed_operands.push_back(operand);
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}
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}
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@ -196,10 +194,8 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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max_width = shared_op->getParam("\\Y_WIDTH").as_int();
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max_width = shared_op->getParam("\\Y_WIDTH").as_int();
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for (auto &operand : muxed_operands) {
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for (auto &operand : muxed_operands)
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operand.sig.extend_u0(max_width, operand.is_signed);
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operand.sig.extend_u0(max_width, operand.is_signed);
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}
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for (const auto& p : ports) {
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for (const auto& p : ports) {
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auto op = p.op;
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auto op = p.op;
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@ -208,11 +204,10 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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module->remove(op);
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module->remove(op);
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}
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}
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for (auto &muxed_op : muxed_operands) {
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for (auto &muxed_op : muxed_operands)
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if (muxed_op.sign != muxed_operands[0].sign) {
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if (muxed_op.sign != muxed_operands[0].sign)
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muxed_op = ExtSigSpec(module->Neg(NEW_ID, muxed_op.sig, muxed_op.is_signed));
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muxed_op = ExtSigSpec(module->Neg(NEW_ID, muxed_op.sig, muxed_op.is_signed));
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}
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}
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RTLIL::SigSpec mux_y = mux->getPort("\\Y");
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RTLIL::SigSpec mux_y = mux->getPort("\\Y");
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RTLIL::SigSpec mux_a = mux->getPort("\\A");
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RTLIL::SigSpec mux_a = mux->getPort("\\A");
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@ -261,7 +256,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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shared_op->setParam("\\Y_WIDTH", conn_width);
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shared_op->setParam("\\Y_WIDTH", conn_width);
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if (shared_op->getPort("\\A") == operand.sig) {
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if (decode_port(shared_op, "\\A", &assign_map) == operand) {
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shared_op->setPort("\\B", mux_to_oper);
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shared_op->setPort("\\B", mux_to_oper);
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shared_op->setParam("\\B_WIDTH", max_width);
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shared_op->setParam("\\B_WIDTH", max_width);
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} else {
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} else {
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@ -299,7 +294,7 @@ void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpe
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auto op = p->op;
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auto op = p->op;
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RTLIL::IdString muxed_port_name = "\\A";
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RTLIL::IdString muxed_port_name = "\\A";
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if (op->getPort("\\A") == shared_operand.sig) {
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if (decode_port(op, "\\A", &assign_map) == shared_operand) {
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muxed_port_name = "\\B";
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muxed_port_name = "\\B";
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}
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}
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@ -486,9 +481,10 @@ struct OptSharePass : public Pass {
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log("\n");
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log("\n");
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log("This pass identifies mutually exclusive cells of the same type that:\n");
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log("This pass identifies mutually exclusive cells of the same type that:\n");
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log(" (a) share an input signal\n");
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log(" (a) share an input signal,\n");
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log(" (b) drive the same $mux, $_MUX_, or $pmux multiplexing cell allowing\n");
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log(" (b) drive the same $mux, $_MUX_, or $pmux multiplexing cell,\n");
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log(" the cell to be merged and the multiplexer to be moved from\n");
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log("\n");
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log("allowing the cell to be merged and the multiplexer to be moved from\n");
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log("multiplexing its output to multiplexing the non-shared input signals.\n");
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log("multiplexing its output to multiplexing the non-shared input signals.\n");
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log("\n");
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log("\n");
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}
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}
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@ -7,7 +7,6 @@ opt merged
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opt_share merged
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opt_share merged
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opt_clean merged
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opt_clean merged
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opt -full
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miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
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miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp opt_share_test merged miter
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sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
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sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter
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