mirror of https://github.com/YosysHQ/yosys.git
Fixed pattern matching in "hierarchy -generate"
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@ -32,7 +32,7 @@ PRIVATE_NAMESPACE_BEGIN
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struct generate_port_decl_t {
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bool input, output;
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RTLIL::IdString portname;
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string portname;
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int index;
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};
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@ -101,7 +101,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
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for (auto &decl : portdecls)
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if (decl.index == 0 && patmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str())) {
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generate_port_decl_t d = decl;
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d.portname = portname;
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d.portname = portname.str();
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d.index = *indices.begin();
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log_assert(!indices.empty());
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indices.erase(d.index);
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