mirror of https://github.com/YosysHQ/yosys.git
Fixing selections
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d1e6de35c3
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06427efb83
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@ -1179,7 +1179,7 @@ void RTLIL::Design::pop_selection()
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std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartials partials, RTLIL::SelectBoxes boxes) const
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{
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bool include_partials = partials == RTLIL::SELECT_ALL;
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bool exclude_boxes = (partials & RTLIL::SB_UNBOXED_ONLY) == 0;
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bool exclude_boxes = (partials & RTLIL::SB_UNBOXED_ONLY) != 0;
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bool ignore_wb = (partials & RTLIL::SB_INCL_WB) != 0;
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std::vector<RTLIL::Module*> result;
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result.reserve(modules_.size());
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@ -1000,7 +1000,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
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static std::string describe_selection_for_assert(RTLIL::Design *design, RTLIL::Selection *sel, bool whole_modules = false)
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{
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std::string desc = "Selection contains:\n";
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for (auto mod : design->selected_modules())
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for (auto mod : design->all_selected_modules())
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{
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if (whole_modules && sel->selected_whole_module(mod->name))
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desc += stringf("%s\n", id2cstr(mod->name));
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@ -1501,7 +1501,7 @@ struct SelectPass : public Pass {
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design->push_selection(work_stack.back());
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RTLIL::Selection *sel = &design->selection();
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sel->optimize(design);
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for (auto mod : design->selected_modules())
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for (auto mod : design->all_selected_modules())
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{
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if (sel->selected_whole_module(mod->name) && list_mode)
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log("%s\n", id2cstr(mod->name));
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@ -1578,7 +1578,7 @@ struct SelectPass : public Pass {
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RTLIL::Selection *sel = &work_stack.back();
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design->push_selection(*sel);
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sel->optimize(design);
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for (auto mod : design->selected_modules()) {
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for (auto mod : design->all_selected_modules()) {
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module_count++;
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for ([[maybe_unused]] auto member_name : mod->selected_members())
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total_count++;
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@ -1777,7 +1777,7 @@ struct LsPass : public Pass {
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{
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std::vector<IdString> matches;
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for (auto mod : design->selected_modules())
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for (auto mod : design->all_selected_modules())
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matches.push_back(mod->name);
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if (!matches.empty()) {
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