mirror of https://github.com/YosysHQ/yosys.git
synth_gatemate: Remove gatemate_bramopt pass
This commit is contained in:
Patrick Urban
Marcelina Kościelnicka
parent
97d03c2b3b
commit
05f24adca9
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@ -1,6 +1,5 @@
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OBJS += techlibs/gatemate/synth_gatemate.o
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OBJS += techlibs/gatemate/synth_gatemate.o
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OBJS += techlibs/gatemate/gatemate_bramopt.o
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$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/iob_map.v))
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$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/iob_map.v))
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$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/reg_map.v))
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$(eval $(call add_share_file,share/gatemate,techlibs/gatemate/reg_map.v))
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@ -1,146 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2021 Cologne Chip AG <support@colognechip.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool binary_pred(SigBit s1, SigBit s2)
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{
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return s1 == s2;
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}
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static void proc_glwren(Module *module)
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{
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std::vector<Cell*> ram_cells;
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// Gather RAM cells
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for (auto cell : module->cells())
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{
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if (cell->type.in(ID(CC_DPSRAM_20K), ID(CC_DPSRAM_40K))) {
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ram_cells.push_back(cell);
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}
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}
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// Convert bitmask signals
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for (auto cell : ram_cells)
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{
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std::vector<SigBit> mska = cell->getPort(ID(A_BM)).to_sigbit_vector();
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std::vector<SigBit> mskb = cell->getPort(ID(B_BM)).to_sigbit_vector();
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// Remove State::S0 from vectors
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mska.erase(std::remove_if(mska.begin(), mska.end(), [](const SigBit & sb){return (sb == State::S0);}), mska.end());
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mskb.erase(std::remove_if(mskb.begin(), mskb.end(), [](const SigBit & sb){return (sb == State::S0);}), mskb.end());
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if (mska.size() + mskb.size() == 0) {
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break;
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}
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if (cell->getParam(ID(RAM_MODE)).decode_string() == "SDP")
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{
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std::vector<SigBit> msk;
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msk.insert(msk.end(), mska.begin(), mska.end());
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msk.insert(msk.end(), mskb.begin(), mskb.end());
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if (std::equal(msk.begin() + 1, msk.end(), msk.begin(), binary_pred))
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{
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if ((cell->getPort(ID(A_WE)) == State::S1) && (cell->getPort(ID(B_WE)) == State::S0))
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{
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cell->setPort(ID(A_WE), msk[0]);
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cell->setPort(ID(B_WE), Const(0, 1));
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// Set bitmask bits to _1_
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cell->setPort(ID(A_BM), Const(State::S1, mska.size()));
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cell->setPort(ID(B_BM), Const(State::S1, mskb.size()));
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}
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}
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}
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else // RAM_MODE == "TDP"
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{
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if (std::equal(mska.begin() + 1, mska.end(), mska.begin(), binary_pred))
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{
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if (cell->getPort(ID(A_WE)) == State::S1)
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{
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// Signals are all equal
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cell->setPort(ID(A_WE), mska[0]);
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cell->setPort(ID(A_BM), Const(State::S1, mska.size()));
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}
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}
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if (std::equal(mskb.begin() + 1, mskb.end(), mskb.begin(), binary_pred))
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{
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if (cell->getPort(ID(B_WE)) == State::S1)
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{
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cell->setPort(ID(B_WE), mskb[0]);
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// Set bitmask bits to _1_
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cell->setPort(ID(B_BM), Const(State::S1, mskb.size()));
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}
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}
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}
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}
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}
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struct GateMateBramOptPass : public Pass {
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GateMateBramOptPass() : Pass("gatemate_bramopt", "GateMate: optimize block RAM cells") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" gatemate_bramopt [options] [selection]\n");
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log("\n");
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log("This pass processes all CC_BRAM_20K and CC_BRAM_40K cells and tries to");
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log("convert its enable bitmask wires to a single global enable signal.");
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log("\n");
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log(" -noglwren\n");
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log(" do not convert bitmasks to single global write enable signals.\n");
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log("\n");
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}
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bool noglwren;
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void clear_flags() override
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{
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noglwren = false;
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing GATEMATE_BRAMOPT pass (optimize block RAM).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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if (args[argidx] == "-noglwren") {
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noglwren = true;
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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if (!noglwren) {
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proc_glwren(module);
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}
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}
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}
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} GateMateBramOptPass;
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PRIVATE_NAMESPACE_END
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@ -264,7 +264,6 @@ struct SynthGateMatePass : public ScriptPass
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"t:$__CC_BRAM_20K_TDP t:$__CC_BRAM_40K_TDP "
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"t:$__CC_BRAM_20K_TDP t:$__CC_BRAM_40K_TDP "
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);
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);
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run("techmap -map +/gatemate/brams_map.v");
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run("techmap -map +/gatemate/brams_map.v");
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run("gatemate_bramopt");
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}
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}
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}
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}
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