mirror of https://github.com/YosysHQ/yosys.git
read_aiger: $lut prefix in front
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05c8858a90
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@ -1001,9 +1001,9 @@ void AigerReader::post_process()
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if (cell->type != "$lut") continue;
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if (cell->type != "$lut") continue;
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auto y_port = cell->getPort("\\Y").as_bit();
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auto y_port = cell->getPort("\\Y").as_bit();
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if (y_port.wire->width == 1)
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if (y_port.wire->width == 1)
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module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str()));
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module->rename(cell, stringf("$lut%s", y_port.wire->name.c_str()));
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else
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else
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module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset));
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module->rename(cell, stringf("$lut%s[%d]", y_port.wire->name.c_str(), y_port.offset));
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}
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}
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}
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}
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