diff --git a/kernel/register.cc b/kernel/register.cc
index bc49f4cb9..ce6eb8018 100644
--- a/kernel/register.cc
+++ b/kernel/register.cc
@@ -1111,18 +1111,20 @@ struct HelpPass : public Pass {
 						log("\n");
 						log("%s\n", help_cell.code.c_str());
 				} else {
+					log("\n    %s %s\n\n", help_cell.name.c_str(), help_cell.ports.c_str());
 					if (help_cell.ver == "2" || help_cell.ver == "2a") {
-						log("\n    %s %s\n\n", help_cell.name.c_str(), help_cell.ports.c_str());
-						if (help_cell.title != "") log("%s\n", help_cell.title.c_str());
+						if (help_cell.title != "") log("%s:\n", help_cell.title.c_str());
 						std::stringstream ss;
 						ss << help_cell.desc;
 						for (std::string line; std::getline(ss, line, '\n');) {
 							if (line != "::") log("%s\n", line.c_str());
 						}
-					} else {
+					} else if (help_cell.desc.length()) {
 						log("%s\n", help_cell.desc.c_str());
+					} else {
+						log("No help message for this cell type found.\n");
 					}
-					log("Run 'help %s+' to display the Verilog model for this cell type.\n", args[1].c_str());
+					log("\nRun 'help %s+' to display the Verilog model for this cell type.\n", args[1].c_str());
 					log("\n");
 				}
 			}
diff --git a/techlibs/common/cellhelp.py b/techlibs/common/cellhelp.py
index 299b7affd..9aa3def93 100644
--- a/techlibs/common/cellhelp.py
+++ b/techlibs/common/cellhelp.py
@@ -84,9 +84,7 @@ for line in fileinput.input():
             simcells_reparse(simHelper)
 
         # check help
-        if not simHelper.desc:
-            simHelper.desc.append("No help message for this cell type found.\n")
-        elif simHelper.ver == "1" and short_filename == "simlib.v" and simHelper.desc[1].startswith('    '):
+        if simHelper.desc and simHelper.ver == "1" and short_filename == "simlib.v" and simHelper.desc[1].startswith('    '):
             simHelper.desc.pop(1)
 
         # check group