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Fixed vhdl2verilog help message

This commit is contained in:
Clifford Wolf 2014-03-01 17:47:19 +01:00
parent 9e99984336
commit 04999f4af0
1 changed files with 2 additions and 3 deletions
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5
frontends/vhdl2verilog/vhdl2verilog.cc
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@ -35,9 +35,8 @@ struct Vhdl2verilogPass : public Pass {
log("\n"); log("\n");
log(" vhdl2verilog [options] <vhdl-file>..\n"); log(" vhdl2verilog [options] <vhdl-file>..\n");
log("\n"); log("\n");
log("This pass looks for subcircuits that are isomorphic to any of the modules\n"); log("This command reads VHDL source files using the 'vhdl2verilog' tool and the\n");
log("in the given map file and replaces them with instances of this modules. The\n"); log("Yosys Verilog frontend.\n");
log("map file can be a verilog source file (*.v) or an ilang file (*.il).\n");
log("\n"); log("\n");
log(" -out <out_file>\n"); log(" -out <out_file>\n");
log(" do not import the vhdl2verilog output. instead write it to the\n"); log(" do not import the vhdl2verilog output. instead write it to the\n");