mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1153 from YosysHQ/dave/fix_multi_mux
memory_dff: Fix checking of feedback mux input when more than one mux
This commit is contained in:
commit
0447794c51
|
@ -17,6 +17,7 @@
|
|||
*
|
||||
*/
|
||||
|
||||
#include <algorithm>
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/sigtools.h"
|
||||
|
||||
|
@ -183,12 +184,12 @@ struct MemoryDffWorker
|
|||
if (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data))
|
||||
{
|
||||
RTLIL::SigSpec en;
|
||||
RTLIL::SigSpec check_q;
|
||||
std::vector<RTLIL::SigSpec> check_q;
|
||||
|
||||
do {
|
||||
bool enable_invert = mux_cells_a.count(sig_data) != 0;
|
||||
Cell *mux = enable_invert ? mux_cells_a.at(sig_data) : mux_cells_b.at(sig_data);
|
||||
check_q = sigmap(mux->getPort(enable_invert ? "\\B" : "\\A"));
|
||||
check_q.push_back(sigmap(mux->getPort(enable_invert ? "\\B" : "\\A")));
|
||||
sig_data = sigmap(mux->getPort("\\Y"));
|
||||
en.append(enable_invert ? module->LogicNot(NEW_ID, mux->getPort("\\S")) : mux->getPort("\\S"));
|
||||
} while (mux_cells_a.count(sig_data) || mux_cells_b.count(sig_data));
|
||||
|
@ -197,7 +198,8 @@ struct MemoryDffWorker
|
|||
if (sigbit_users_count[bit] > 1)
|
||||
goto skip_ff_after_read_merging;
|
||||
|
||||
if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) && sig_data == check_q)
|
||||
if (find_sig_before_dff(sig_data, clk_data, clk_polarity, true) && clk_data != RTLIL::SigSpec(RTLIL::State::Sx) &&
|
||||
std::all_of(check_q.begin(), check_q.end(), [&](const SigSpec &cq) {return cq == sig_data; }))
|
||||
{
|
||||
disconnect_dff(sig_data);
|
||||
cell->setPort("\\CLK", clk_data);
|
||||
|
|
|
@ -0,0 +1,16 @@
|
|||
// expect-wr-ports 1
|
||||
// expect-rd-ports 1
|
||||
// expect-no-rd-clk
|
||||
|
||||
module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
|
||||
|
||||
reg [7:0] bram[0:255];
|
||||
(* keep *) reg dummy;
|
||||
|
||||
always @(posedge clk) begin
|
||||
rdata <= re ? (reset ? 8'b0 : bram[addr]) : rdata;
|
||||
if (we)
|
||||
bram[addr] <= wdata;
|
||||
end
|
||||
|
||||
endmodule
|
|
@ -31,6 +31,10 @@ for f in `egrep -l 'expect-(wr-ports|rd-ports|rd-clk)' *.v`; do
|
|||
grep -q "connect \\\\RD_CLK \\$(gawk '/expect-rd-clk/ { print $3; }' $f)\$" ${f%.v}.dmp ||
|
||||
{ echo " ERROR: Unexpected read clock."; false; }
|
||||
fi
|
||||
if grep -q expect-no-rd-clk $f; then
|
||||
grep -q "connect \\\\RD_CLK 1'x\$" ${f%.v}.dmp ||
|
||||
{ echo " ERROR: Expected no read clock."; false; }
|
||||
fi
|
||||
echo " ok."
|
||||
done
|
||||
|
||||
|
|
Loading…
Reference in New Issue