mirror of https://github.com/YosysHQ/yosys.git
opt_lut: Remove leftover `-dlogic` help
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@ -529,12 +529,6 @@ struct OptLutPass : public Pass {
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log("\n");
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log("\n");
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log("This pass combines cascaded $lut cells with unused inputs.\n");
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log("This pass combines cascaded $lut cells with unused inputs.\n");
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log("\n");
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log("\n");
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log(" -dlogic <type>:<cell-port>=<LUT-input>[:<cell-port>=<LUT-input>...]\n");
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log(" preserve connections to dedicated logic cell <type> that has ports\n");
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log(" <cell-port> connected to LUT inputs <LUT-input>. this includes\n");
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log(" the case where both LUT and dedicated logic input are connected to\n");
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log(" the same constant.\n");
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log("\n");
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log(" -tech ice40\n");
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log(" -tech ice40\n");
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log(" treat the design as a LUT-mapped circuit for the iCE40 architecture\n");
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log(" treat the design as a LUT-mapped circuit for the iCE40 architecture\n");
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log(" and preserve connections to SB_CARRY as appropriate\n");
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log(" and preserve connections to SB_CARRY as appropriate\n");
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