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booth: Fix vacancy check when summing down result 

In commit fedd12261 ("booth: Move away from explicit `Wire` pointers")
a bug was introduced when checking for vacant slots in arrays holding
some intermediate results. Non-wire SigBit values were taken to imply
a vacant slot, but actually a constant one can make its way into those
results, if the multiplier cell configuration is just right. Fix the
vacancy check to address the bug.
This commit is contained in:
Martin Povišer 2023-10-04 23:21:40 +02:00
parent 3e02b63ee1
commit 0434f9d3d1
1 changed files with 3 additions and 3 deletions
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6
passes/techmap/booth.cc
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@ -533,7 +533,7 @@ struct BoothPassWorker {
// get the bits in this column. // get the bits in this column.
SigSpec column_bits; SigSpec column_bits;
for (int row_ix = 0; row_ix < row_size; row_ix++) { for (int row_ix = 0; row_ix < row_size; row_ix++) {
if (bits_to_reduce[row_ix][column_ix].wire) if (bits_to_reduce[row_ix][column_ix] != State::S0)
column_bits.append(bits_to_reduce[row_ix][column_ix]); column_bits.append(bits_to_reduce[row_ix][column_ix]);
} }
for (auto c : carry_bits_to_add_to_next_column) { for (auto c : carry_bits_to_add_to_next_column) {
@ -750,7 +750,7 @@ struct BoothPassWorker {
SigSpec first_csa_ips; SigSpec first_csa_ips;
// get the first 3 inputs, if possible // get the first 3 inputs, if possible
for (var_ix = 0; var_ix < column_bits.size() && first_csa_ips.size() != 3; var_ix++) { for (var_ix = 0; var_ix < column_bits.size() && first_csa_ips.size() != 3; var_ix++) {
if (column_bits[var_ix].is_wire()) if (column_bits[var_ix] != State::S0)
first_csa_ips.append(column_bits[var_ix]); first_csa_ips.append(column_bits[var_ix]);
} }
@ -782,7 +782,7 @@ struct BoothPassWorker {
// get the next two variables to sum // get the next two variables to sum
for (; var_ix <= column_bits.size() - 1 && csa_ips.size() < 2;) { for (; var_ix <= column_bits.size() - 1 && csa_ips.size() < 2;) {
// skip any empty bits // skip any empty bits
if (column_bits[var_ix].is_wire()) if (column_bits[var_ix] != State::S0)
csa_ips.append(column_bits[var_ix]); csa_ips.append(column_bits[var_ix]);
var_ix++; var_ix++;
} }