mirror of https://github.com/YosysHQ/yosys.git
Reformat so it shows up/looks nice when "help $alu" and "help $alu+"
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@ -532,13 +532,17 @@ endmodule
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// --------------------------------------------------------
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// --------------------------------------------------------
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// Lookahead carry unit
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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// A building block dedicated to fast computation of carry-bits
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//-
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// used in binary arithmetic operations. By replacing the ripple
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//- $lcu (P, G, CI, CO)
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// carry structure used in full-adder blocks, the more significant
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//-
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// bits of the sum can be expected to be computed more quickly.
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//- Lookahead carry unit
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// Typically created during `techmap` of $alu cells
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//- A building block dedicated to fast computation of carry-bits used in binary
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// (see the "_90_alu" rule in +/techmap.v)
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//- arithmetic operations. By replacing the ripple carry structure used in full-adder
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//- blocks, the more significant bits of the sum can be expected to be computed more
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//- quickly.
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//- Typically created during `techmap` of $alu cells (see the "_90_alu" rule in
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//- +/techmap.v).
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module \$lcu (P, G, CI, CO);
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module \$lcu (P, G, CI, CO);
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parameter WIDTH = 1;
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parameter WIDTH = 1;
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@ -563,12 +567,17 @@ endmodule
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// --------------------------------------------------------
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// --------------------------------------------------------
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// Arithmetic logic unit
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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// A building block supporting both binary addition/subtraction
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//-
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// operations, and indirectly, comparison operations.
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//- $alu (A, B, CI, BI, X, Y, CO)
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// Typically created by the `alumacc` pass, which transforms
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//-
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// $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
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//- Arithmetic logic unit.
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// cells into this $alu cell.
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//- A building block supporting both binary addition/subtraction operations, and
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//- indirectly, comparison operations.
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//- Typically created by the `alumacc` pass, which transforms:
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//- $add, $sub, $lt, $le, $ge, $gt, $eq, $eqx, $ne, $nex
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//- cells into this $alu cell.
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//-
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module \$alu (A, B, CI, BI, X, Y, CO);
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module \$alu (A, B, CI, BI, X, Y, CO);
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parameter A_SIGNED = 0;
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parameter A_SIGNED = 0;
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