riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Cleanups in freduce command

This commit is contained in:
Clifford Wolf 2014-01-03 17:50:39 +01:00
parent 7354a1718e
commit 03f0ab9de2
1 changed files with 5 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
passes/sat/freduce.cc
View File

@ -441,8 +441,6 @@ struct FreduceWorker
int bits_count = 0; int bits_count = 0;
std::map<std::vector<RTLIL::SigBit>, std::vector<RTLIL::SigBit>> buckets; std::map<std::vector<RTLIL::SigBit>, std::vector<RTLIL::SigBit>> buckets;
buckets[std::vector<RTLIL::SigBit>()].push_back(RTLIL::SigBit(RTLIL::State::S0));
buckets[std::vector<RTLIL::SigBit>()].push_back(RTLIL::SigBit(RTLIL::State::S1));
for (auto &batch : batches) for (auto &batch : batches)
{ {
for (auto &bit : batch) for (auto &bit : batch)
@ -464,6 +462,11 @@ struct FreduceWorker
} }
log(" Sorted %d signal bits into %d buckets.\n", bits_count, int(buckets.size())); log(" Sorted %d signal bits into %d buckets.\n", bits_count, int(buckets.size()));
if (buckets.count(std::vector<RTLIL::SigBit>()) != 0) {
buckets[std::vector<RTLIL::SigBit>()].push_back(RTLIL::SigBit(RTLIL::State::S0));
buckets[std::vector<RTLIL::SigBit>()].push_back(RTLIL::SigBit(RTLIL::State::S1));
}
std::vector<std::vector<equiv_bit_t>> equiv; std::vector<std::vector<equiv_bit_t>> equiv;
for (auto &bucket : buckets) for (auto &bucket : buckets)
{ {