riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Run "clean" on mapped_mod in its own design

This commit is contained in:
Eddie Hung 2019-08-01 22:21:30 -07:00
parent 3090da2d98
commit 03ec8d6551
2 changed files with 11 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

34
frontends/aiger/aigerparse.cc
View File

@ -337,7 +337,7 @@ static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned litera
return wire; return wire;
} }
void AigerReader::parse_xaiger() void AigerReader::parse_xaiger(const dict<int,IdString> &box_lookup)
{ {
std::string header; std::string header;
f >> header; f >> header;
@ -373,21 +373,6 @@ void AigerReader::parse_xaiger()
if (n0) if (n0)
module->connect(n0, RTLIL::S0); module->connect(n0, RTLIL::S0);
dict<int,IdString> box_lookup;
for (auto m : design->modules()) {
auto it = m->attributes.find("\\abc_box_id");
if (it == m->attributes.end())
continue;
if (m->name.begins_with("$paramod"))
continue;
auto id = it->second.as_int();
auto r = box_lookup.insert(std::make_pair(id, m->name));
if (!r.second)
log_error("Module '%s' has the same abc_box_id = %d value as '%s'.\n",
log_id(m), id, log_id(r.first->second));
log_assert(r.second);
}
// Parse footer (symbol table, comments, etc.) // Parse footer (symbol table, comments, etc.)
std::string s; std::string s;
bool comment_seen = false; bool comment_seen = false;
@ -986,16 +971,17 @@ void AigerReader::post_process()
} }
module->fixup_ports(); module->fixup_ports();
// Insert into a new (temporary) design so that "clean" will only
// operate (and run checks on) this one module
RTLIL::Design *mapped_design = new RTLIL::Design;
mapped_design->add(module);
Pass::call(mapped_design, "clean");
mapped_design->modules_.erase(module->name);
delete mapped_design;
design->add(module); design->add(module);
design->selection_stack.emplace_back(false);
RTLIL::Selection& sel = design->selection_stack.back();
sel.select(module);
Pass::call(design, "clean");
design->selection_stack.pop_back();
for (auto cell : module->cells().to_vector()) { for (auto cell : module->cells().to_vector()) {
if (cell->type != "$lut") continue; if (cell->type != "$lut") continue;
auto y_port = cell->getPort("\\Y").as_bit(); auto y_port = cell->getPort("\\Y").as_bit();

2
frontends/aiger/aigerparse.h
View File

@ -47,7 +47,7 @@ struct AigerReader
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports); AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
void parse_aiger(); void parse_aiger();
void parse_xaiger(); void parse_xaiger(const dict<int,IdString> &box_lookup);
void parse_aiger_ascii(); void parse_aiger_ascii();
void parse_aiger_binary(); void parse_aiger_binary();
void post_process(); void post_process();