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Escape Verilog identifiers for legality outside of Yosys

This commit is contained in:
Eddie Hung 2019-10-01 13:05:56 -07:00
parent 1b96d29174
commit 03ebe43e3e
1 changed files with 48 additions and 48 deletions
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96
techlibs/xilinx/cells_sim.v
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@ -258,9 +258,9 @@ module FDRE (
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_R_INVERTED = 1'b0; parameter [0:0] IS_R_INVERTED = 1'b0;
initial Q <= INIT; initial Q <= INIT;
wire $currQ; wire \$currQ ;
reg $nextQ; reg \$nextQ ;
always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ; always @* if (R == !IS_R_INVERTED) $nextQ = 1'b0; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
`ifdef _ABC `ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial // `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@ -277,12 +277,12 @@ module FDRE (
// (which, combined with this spell type, encodes to `abc9' // (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together) // which flops may be merged together)
wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED}; wire [3:0] $abc9_control = {CE, IS_D_INVERTED, R, IS_R_INVERTED};
always @* Q = $nextQ; always @* Q = \$nextQ ;
`else `else
assign $currQ = Q; assign $currQ = Q;
generate case (|IS_C_INVERTED) generate case (|IS_C_INVERTED)
1'b0: always @(posedge C) Q <= $nextQ; 1'b0: always @(posedge C) Q <= \$nextQ ;
1'b1: always @(negedge C) Q <= $nextQ; 1'b1: always @(negedge C) Q <= \$nextQ ;
endcase endgenerate endcase endgenerate
`endif `endif
endmodule endmodule
@ -297,9 +297,9 @@ module FDRE_1 (
); );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q <= INIT; initial Q <= INIT;
wire $currQ; wire \$currQ ;
reg $nextQ; reg \$nextQ ;
always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = $currQ; always @* if (R) Q <= 1'b0; else if (CE) Q <= D; else $nextQ = \$currQ ;
`ifdef _ABC `ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial // `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@ -316,10 +316,10 @@ module FDRE_1 (
// (which, combined with this spell type, encodes to `abc9' // (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together) // which flops may be merged together)
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */}; wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, R, 1'b0 /* IS_R_INVERTED */};
always @* Q = $nextQ; always @* Q = \$nextQ ;
`else `else
assign $currQ = Q; assign $currQ = Q;
always @(negedge C) Q <= $nextQ; always @(negedge C) Q <= \$nextQ ;
`endif `endif
endmodule endmodule
@ -341,9 +341,9 @@ module FDCE (
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_CLR_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0;
initial Q <= INIT; initial Q <= INIT;
wire $currQ; wire \$currQ ;
reg $nextQ; reg \$nextQ ;
always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ; always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
`ifdef _ABC `ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial // `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@ -362,14 +362,14 @@ module FDCE (
// (which, combined with this spell type, encodes to `abc9' // (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together) // which flops may be merged together)
wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED}; wire [3:0] $abc9_control = {CE, IS_D_INVERTED, CLR, IS_CLR_INVERTED};
always @* Q = $nextQ; always @* Q = \$nextQ ;
`else `else
assign $currQ = Q; assign $currQ = Q;
generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED}) generate case ({|IS_C_INVERTED, |IS_CLR_INVERTED})
2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ; 2'b00: always @(posedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ; 2'b01: always @(posedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= $nextQ; 2'b10: always @(negedge C, posedge CLR) if ( CLR) Q <= 1'b0; else Q <= \$nextQ ;
2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= $nextQ; 2'b11: always @(negedge C, negedge CLR) if (!CLR) Q <= 1'b0; else Q <= \$nextQ ;
endcase endgenerate endcase endgenerate
`endif `endif
endmodule endmodule
@ -384,9 +384,9 @@ module FDCE_1 (
); );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
initial Q <= INIT; initial Q <= INIT;
wire $currQ; wire \$currQ ;
reg $nextQ; reg \$nextQ ;
always @* if (CE) Q <= D; else $nextQ = $currQ; always @* if (CE) Q <= D; else $nextQ = \$currQ ;
`ifdef _ABC `ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial // `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@ -405,10 +405,10 @@ module FDCE_1 (
// (which, combined with this spell type, encodes to `abc9' // (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together) // which flops may be merged together)
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */}; wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, CLR, 1'b0 /* IS_CLR_INVERTED */};
always @* Q = $nextQ; always @* Q = \$nextQ ;
`else `else
assign $currQ = Q; assign $currQ = Q;
always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= $nextQ; always @(negedge C, posedge CLR) if (CLR) Q <= 1'b0; else Q <= \$nextQ ;
`endif `endif
endmodule endmodule
@ -430,9 +430,9 @@ module FDPE (
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_PRE_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0;
initial Q <= INIT; initial Q <= INIT;
wire $currQ; wire \$currQ ;
reg $nextQ; reg \$nextQ ;
always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = $currQ; always @* if (CE) Q <= D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
`ifdef _ABC `ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial // `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@ -451,14 +451,14 @@ module FDPE (
// (which, combined with this spell type, encodes to `abc9' // (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together) // which flops may be merged together)
wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED}; wire [3:0] $abc9_control = {CE, IS_D_INVERTED, PRE, IS_PRE_INVERTED};
always @* Q = $nextQ; always @* Q = \$nextQ ;
`else `else
assign $currQ = Q; assign $currQ = Q;
generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED}) generate case ({|IS_C_INVERTED, |IS_PRE_INVERTED})
2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ; 2'b00: always @(posedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ; 2'b01: always @(posedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= $nextQ; 2'b10: always @(negedge C, posedge PRE) if ( PRE) Q <= 1'b1; else Q <= \$nextQ ;
2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= $nextQ; 2'b11: always @(negedge C, negedge PRE) if (!PRE) Q <= 1'b1; else Q <= \$nextQ ;
endcase endgenerate endcase endgenerate
`endif `endif
endmodule endmodule
@ -473,9 +473,9 @@ module FDPE_1 (
); );
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q <= INIT; initial Q <= INIT;
wire $currQ; wire \$currQ ;
reg $nextQ; reg \$nextQ ;
always @* if (CE) Q <= D; else $nextQ = $currQ; always @* if (CE) Q <= D; else $nextQ = \$currQ ;
`ifdef _ABC `ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial // `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@ -494,10 +494,10 @@ module FDPE_1 (
// (which, combined with this spell type, encodes to `abc9' // (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together) // which flops may be merged together)
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */}; wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, PRE, 1'b0 /* IS_PRE_INVERTED */};
always @* Q = $nextQ; always @* Q = \$nextQ ;
`else `else
assign $currQ = Q; assign $currQ = Q;
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= $nextQ; always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else Q <= \$nextQ ;
`endif `endif
endmodule endmodule
@ -519,9 +519,9 @@ module FDSE (
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
parameter [0:0] IS_S_INVERTED = 1'b0; parameter [0:0] IS_S_INVERTED = 1'b0;
initial Q <= INIT; initial Q <= INIT;
wire $currQ; wire \$currQ ;
reg $nextQ; reg \$nextQ ;
always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = $currQ; always @* if (S == !IS_S_INVERTED) $nextQ = 1'b1; else if (CE) $nextQ = D ^ IS_D_INVERTED; else $nextQ = \$currQ ;
`ifdef _ABC `ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial // `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@ -538,12 +538,12 @@ module FDSE (
// (which, combined with this spell type, encodes to `abc9' // (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together) // which flops may be merged together)
wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED}; wire [3:0] $abc9_control = {CE, IS_D_INVERTED, S, IS_S_INVERTED};
always @* Q = $nextQ; always @* Q = \$nextQ ;
`else `else
assign $currQ = Q; assign $currQ = Q;
generate case (|IS_C_INVERTED) generate case (|IS_C_INVERTED)
1'b0: always @(posedge C) Q <= $nextQ; 1'b0: always @(posedge C) Q <= \$nextQ ;
1'b1: always @(negedge C) Q <= $nextQ; 1'b1: always @(negedge C) Q <= \$nextQ ;
endcase endgenerate endcase endgenerate
`endif `endif
endmodule endmodule
@ -558,9 +558,9 @@ module FDSE_1 (
); );
parameter [0:0] INIT = 1'b1; parameter [0:0] INIT = 1'b1;
initial Q <= INIT; initial Q <= INIT;
wire $currQ; wire \$currQ ;
reg $nextQ; reg \$nextQ ;
always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = $currQ; always @* if (S) $nextQ = 1'b1; else if (CE) $nextQ = D; else $nextQ = \$currQ ;
`ifdef _ABC `ifdef _ABC
// `abc9' requires that complex flops be split into a combinatorial // `abc9' requires that complex flops be split into a combinatorial
// box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v) // box (this module) feeding a simple flop ($_ABC_FF_ in abc_map.v)
@ -577,10 +577,10 @@ module FDSE_1 (
// (which, combined with this spell type, encodes to `abc9' // (which, combined with this spell type, encodes to `abc9'
// which flops may be merged together) // which flops may be merged together)
wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */}; wire [3:0] $abc9_control = {CE, 1'b0 /* IS_D_INVERTED */, S, 1'b0 /* IS_S_INVERTED */};
always @* Q = $nextQ; always @* Q = \$nextQ ;
`else `else
assign $currQ = Q; assign $currQ = Q;
always @(negedge C) Q <= $nextQ; always @(negedge C) Q <= \$nextQ ;
`endif `endif
endmodule endmodule