mirror of https://github.com/YosysHQ/yosys.git
clk2fflogic: Consistently treat async control signals as negative hold.
This fixes some dfflegalize equivalence checks, and breaks others — and I strongly suspect the others are due to bad support for multiple async inputs in `proc` (in particular, lack of proper support for dlatchsr and sketchy circuits on dffsr control inputs).
This commit is contained in:
Marcelina Kościelnicka
parent
e9c2c1b717
commit
03e28f7ab4
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@ -36,6 +36,30 @@ struct Clk2fflogicPass : public Pass {
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log("multiple clocks.\n");
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log("\n");
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}
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SigSpec wrap_async_control(Module *module, SigSpec sig, bool polarity) {
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Wire *past_sig = module->addWire(NEW_ID, GetSize(sig));
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module->addFf(NEW_ID, sig, past_sig);
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if (polarity)
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sig = module->Or(NEW_ID, sig, past_sig);
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else
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sig = module->And(NEW_ID, sig, past_sig);
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if (polarity)
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return sig;
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else
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return module->Not(NEW_ID, sig);
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}
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SigSpec wrap_async_control_gate(Module *module, SigSpec sig, bool polarity) {
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Wire *past_sig = module->addWire(NEW_ID);
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module->addFfGate(NEW_ID, sig, past_sig);
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if (polarity)
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sig = module->OrGate(NEW_ID, sig, past_sig);
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else
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sig = module->AndGate(NEW_ID, sig, past_sig);
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if (polarity)
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return sig;
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else
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return module->NotGate(NEW_ID, sig);
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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// bool flag_noinit = false;
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@ -153,7 +177,7 @@ struct Clk2fflogicPass : public Pass {
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cell->setPort(ID::WR_DATA, wr_data_port);
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}
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if (cell->type.in(ID($dlatch), ID($dlatchsr)))
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if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)))
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{
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bool enpol = cell->parameters[ID::EN_POLARITY].as_bool();
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@ -165,32 +189,32 @@ struct Clk2fflogicPass : public Pass {
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log_id(module), log_id(cell), log_id(cell->type),
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log_signal(sig_en), log_signal(sig_d), log_signal(sig_q));
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sig_en = wrap_async_control(module, sig_en, enpol);
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Wire *past_q = module->addWire(NEW_ID, GetSize(sig_q));
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module->addFf(NEW_ID, sig_q, past_q);
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if (cell->type == ID($dlatch))
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{
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if (enpol)
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module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
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else
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module->addMux(NEW_ID, sig_d, past_q, sig_en, sig_q);
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module->addMux(NEW_ID, past_q, sig_d, sig_en, sig_q);
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}
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else if (cell->type == ID($adlatch))
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{
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SigSpec t = module->Mux(NEW_ID, past_q, sig_d, sig_en);
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SigSpec arst = wrap_async_control(module, cell->getPort(ID::ARST), cell->parameters[ID::ARST_POLARITY].as_bool());
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Const rstval = cell->parameters[ID::ARST_VALUE];
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module->addMux(NEW_ID, t, rstval, arst, sig_q);
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}
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else
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{
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SigSpec t;
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if (enpol)
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t = module->Mux(NEW_ID, past_q, sig_d, sig_en);
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else
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t = module->Mux(NEW_ID, sig_d, past_q, sig_en);
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SigSpec t = module->Mux(NEW_ID, past_q, sig_d, sig_en);
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SigSpec s = cell->getPort(ID::SET);
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if (!cell->parameters[ID::SET_POLARITY].as_bool())
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s = module->Not(NEW_ID, s);
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SigSpec s = wrap_async_control(module, cell->getPort(ID::SET), cell->parameters[ID::SET_POLARITY].as_bool());
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t = module->Or(NEW_ID, t, s);
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SigSpec c = cell->getPort(ID::CLR);
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if (cell->parameters[ID::CLR_POLARITY].as_bool())
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c = module->Not(NEW_ID, c);
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SigSpec c = wrap_async_control(module, cell->getPort(ID::CLR), cell->parameters[ID::CLR_POLARITY].as_bool());
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c = module->Not(NEW_ID, c);
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module->addAnd(NEW_ID, t, c, sig_q);
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}
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@ -279,55 +303,30 @@ struct Clk2fflogicPass : public Pass {
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if (cell->type == ID($adff))
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{
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SigSpec arst = cell->getPort(ID::ARST);
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SigSpec arst = wrap_async_control(module, cell->getPort(ID::ARST), cell->parameters[ID::ARST_POLARITY].as_bool());
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SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
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Const rstval = cell->parameters[ID::ARST_VALUE];
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Wire *past_arst = module->addWire(NEW_ID);
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module->addFf(NEW_ID, arst, past_arst);
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if (cell->parameters[ID::ARST_POLARITY].as_bool())
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arst = module->LogicOr(NEW_ID, arst, past_arst);
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else
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arst = module->LogicAnd(NEW_ID, arst, past_arst);
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if (cell->parameters[ID::ARST_POLARITY].as_bool())
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module->addMux(NEW_ID, qval, rstval, arst, sig_q);
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else
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module->addMux(NEW_ID, rstval, qval, arst, sig_q);
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module->addMux(NEW_ID, qval, rstval, arst, sig_q);
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}
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else
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if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
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ID($_DFF_PP0_), ID($_DFF_PP1_), ID($_DFF_PN0_), ID($_DFF_PN1_)))
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{
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SigSpec arst = cell->getPort(ID::R);
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SigSpec arst = wrap_async_control_gate(module, cell->getPort(ID::R), cell->type[7] == 'P');
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SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
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SigBit rstval = (cell->type[8] == '1');
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Wire *past_arst = module->addWire(NEW_ID);
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module->addFfGate(NEW_ID, arst, past_arst);
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if (cell->type[7] == 'P')
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arst = module->OrGate(NEW_ID, arst, past_arst);
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else
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arst = module->AndGate(NEW_ID, arst, past_arst);
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if (cell->type[7] == 'P')
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module->addMuxGate(NEW_ID, qval, rstval, arst, sig_q);
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else
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module->addMuxGate(NEW_ID, rstval, qval, arst, sig_q);
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module->addMuxGate(NEW_ID, qval, rstval, arst, sig_q);
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}
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else
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if (cell->type == ID($dffsr))
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{
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SigSpec qval = module->Mux(NEW_ID, past_q, past_d, clock_edge);
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SigSpec setval = cell->getPort(ID::SET);
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SigSpec clrval = cell->getPort(ID::CLR);
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if (!cell->parameters[ID::SET_POLARITY].as_bool())
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setval = module->Not(NEW_ID, setval);
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if (cell->parameters[ID::CLR_POLARITY].as_bool())
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clrval = module->Not(NEW_ID, clrval);
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SigSpec setval = wrap_async_control(module, cell->getPort(ID::SET), cell->parameters[ID::SET_POLARITY].as_bool());
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SigSpec clrval = wrap_async_control(module, cell->getPort(ID::CLR), cell->parameters[ID::CLR_POLARITY].as_bool());
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clrval = module->Not(NEW_ID, clrval);
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qval = module->Or(NEW_ID, qval, setval);
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module->addAnd(NEW_ID, qval, clrval, sig_q);
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}
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@ -336,15 +335,10 @@ struct Clk2fflogicPass : public Pass {
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ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_)))
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{
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SigSpec qval = module->MuxGate(NEW_ID, past_q, past_d, clock_edge);
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SigSpec setval = cell->getPort(ID::S);
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SigSpec clrval = cell->getPort(ID::R);
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if (cell->type[9] != 'P')
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setval = module->Not(NEW_ID, setval);
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if (cell->type[10] == 'P')
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clrval = module->Not(NEW_ID, clrval);
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SigSpec setval = wrap_async_control_gate(module, cell->getPort(ID::S), cell->type[9] == 'P');
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SigSpec clrval = wrap_async_control_gate(module, cell->getPort(ID::R), cell->type[10] == 'P');
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clrval = module->NotGate(NEW_ID, clrval);
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qval = module->OrGate(NEW_ID, qval, setval);
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module->addAndGate(NEW_ID, qval, clrval, sig_q);
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}
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@ -39,8 +39,8 @@ design -save orig
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flatten
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFF_PP0_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ x
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
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# Convert everything to ADFFs.
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@ -45,10 +45,10 @@ equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_DLATCH_P_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_DLATCH_P_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_DLATCH_P_ 1
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
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# Convert everything to ADFFs.
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@ -22,7 +22,7 @@ EOT
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design -save orig
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flatten
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
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# Convert everything to ADLATCHs.
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@ -25,8 +25,8 @@ equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
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# Convert everything to ADLATCHs.
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@ -49,10 +49,10 @@ flatten
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP0P_ 1 -cell $_SR_PP_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 0 -cell $_SR_PP_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFE_PP1P_ 1 -cell $_SR_PP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
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# Convert everything to ADFFs.
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@ -9,12 +9,12 @@ endmodule
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EOT
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design -save orig
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ x
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ x
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x
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# Convert everything to SRs.
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@ -21,18 +21,18 @@ EOT
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design -save orig
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flatten
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
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equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ 1
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ 1
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ 1
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ 1
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ 1
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 0
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#equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ 1
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# Convert everything to SRs.
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