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Fix typo, and have !{PRE,CLR} behave as CE

This commit is contained in:
Eddie Hung 2019-07-10 17:15:49 -07:00
parent 7b2599cb94
commit 0372c900e8
1 changed files with 14 additions and 14 deletions
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28
techlibs/xilinx/abc_ff.v
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@ -44,14 +44,14 @@ module FDCE (output reg Q, input C, CE, D, CLR);
wire \$nextQ , \$currQ ; wire \$nextQ , \$currQ ;
\$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)); \$__ABC_FDCE #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q)); \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
endmodule endmodule
module FDCE_1 (output reg Q, input C, CE, D, CLR); module FDCE_1 (output reg Q, input C, CE, D, CLR);
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
wire \$nextQ , \$currQ ; wire \$nextQ , \$currQ ;
\$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR)); \$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .CLR(CLR));
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ )); \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q)); \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
endmodule endmodule
module FDPE (output reg Q, input C, CE, D, PRE); module FDPE (output reg Q, input C, CE, D, PRE);
@ -64,9 +64,9 @@ module FDPE (output reg Q, input C, CE, D, PRE);
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
generate generate
if (IS_PRE_INVERTED) if (IS_PRE_INVERTED)
\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q)); \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
else else
\$__ABC_MUX_ abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q)); \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b1), .B(\$currQ ), .S(PRE), .Y(Q));
endgenerate endgenerate
endmodule endmodule
module FDPE_1 (output reg Q, input C, CE, D, CLR); module FDPE_1 (output reg Q, input C, CE, D, CLR);
@ -74,7 +74,7 @@ module FDPE_1 (output reg Q, input C, CE, D, CLR);
wire \$nextQ , \$currQ ; wire \$nextQ , \$currQ ;
\$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE)); \$__ABC_FDCE_1 #(.INIT(|0)) _TECHMAP_REPLACE_ (.D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .PRE(PRE));
\$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q)); \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(Q));
\$__ABC_MUX_ abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q)); \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b1), .S(PRE), .Y(Q));
endmodule endmodule
`ifndef _ABC `ifndef _ABC
@ -82,7 +82,7 @@ module \$__ABC_FF_ (input C, D, output Q);
endmodule endmodule
(* abc_box_id = 1000 *) (* abc_box_id = 1000 *)
module \$__ABC_FD_ASYNC_MUX_ (input A, B, S, output Q); module \$__ABC_FD_ASYNC_MUX (input A, B, S, output Q);
// assign Q = S ? B : A; // assign Q = S ? B : A;
endmodule endmodule
@ -109,8 +109,8 @@ module \$__ABC_FDCE (output Q, input C, CE, D, CLR, \$pastQ );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0; //parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
//parameter [0:0] IS_CLR_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0;
assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ; assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule endmodule
(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *) (* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1,D,Q,\\$pastQ" *)
@ -118,8 +118,8 @@ module \$__ABC_FDCE_1 (output Q, input C, CE, D, CLR, \$pastQ );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0; //parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
//parameter [0:0] IS_CLR_INVERTED = 1'b0; parameter [0:0] IS_CLR_INVERTED = 1'b0;
assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ; assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule endmodule
(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *) (* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE,D,Q,\\$pastQ" *)
@ -127,8 +127,8 @@ module \$__ABC_FDPE (output Q, input C, CE, D, PRE, \$pastQ );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0; //parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
//parameter [0:0] IS_PRE_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0;
assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ; assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule endmodule
(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *) (* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1,D,Q,\\$pastQ" *)
@ -136,8 +136,8 @@ module \$__ABC_FDPE_1 (output Q, input C, CE, D, PRE, \$pastQ );
parameter [0:0] INIT = 1'b0; parameter [0:0] INIT = 1'b0;
//parameter [0:0] IS_C_INVERTED = 1'b0; //parameter [0:0] IS_C_INVERTED = 1'b0;
parameter [0:0] IS_D_INVERTED = 1'b0; parameter [0:0] IS_D_INVERTED = 1'b0;
//parameter [0:0] IS_PRE_INVERTED = 1'b0; parameter [0:0] IS_PRE_INVERTED = 1'b0;
assign Q = CE ? (D ^ IS_D_INVERTED) : \$pastQ ; assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
endmodule endmodule
`endif `endif