Re-created command-reference-manual.tex, copied some doc fixes to online help

backends/verilog/verilog_backend.cc

@@ -1315,14 +1315,14 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 }
 
 struct VerilogBackend : public Backend {
-	VerilogBackend() : Backend("verilog", "write design to verilog file") { }
+	VerilogBackend() : Backend("verilog", "write design to Verilog file") { }
 	virtual void help()
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 		log("    write_verilog [options] [filename]\n");
 		log("\n");
-		log("Write the current design to a verilog file.\n");
+		log("Write the current design to a Verilog file.\n");
 		log("\n");
 		log("    -norename\n");
 		log("        without this option all internal object names (the ones with a dollar\n");
@@ -1336,7 +1336,7 @@ struct VerilogBackend : public Backend {
 		log("        with this option attributes are included as comments in the output\n");
 		log("\n");
 		log("    -noexpr\n");
-		log("        without this option all internal cells are converted to verilog\n");
+		log("        without this option all internal cells are converted to Verilog\n");
 		log("        expressions.\n");
 		log("\n");
 		log("    -blackboxes\n");

frontends/verilog/verilog_frontend.cc

@@ -40,14 +40,14 @@ static std::vector<std::string> verilog_defaults;
 static std::list<std::vector<std::string>> verilog_defaults_stack;
 
 struct VerilogFrontend : public Frontend {
-	VerilogFrontend() : Frontend("verilog", "read modules from verilog file") { }
+	VerilogFrontend() : Frontend("verilog", "read modules from Verilog file") { }
 	virtual void help()
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
 		log("    read_verilog [options] [filename]\n");
 		log("\n");
-		log("Load modules from a verilog file to the current design. A large subset of\n");
+		log("Load modules from a Verilog file to the current design. A large subset of\n");
 		log("Verilog-2005 is supported.\n");
 		log("\n");
 		log("    -sv\n");
@@ -65,7 +65,7 @@ struct VerilogFrontend : public Frontend {
 		log("        dump abstract syntax tree (after simplification)\n");
 		log("\n");
 		log("    -dump_vlog\n");
-		log("        dump ast as verilog code (after simplification)\n");
+		log("        dump ast as Verilog code (after simplification)\n");
 		log("\n");
 		log("    -yydebug\n");
 		log("        enable parser debug output\n");
@@ -102,7 +102,7 @@ struct VerilogFrontend : public Frontend {
 		log("        memories to registers directly in the front-end.\n");
 		log("\n");
 		log("    -ppdump\n");
-		log("        dump verilog code after pre-processor\n");
+		log("        dump Verilog code after pre-processor\n");
 		log("\n");
 		log("    -nopp\n");
 		log("        do not run the pre-processor\n");
@@ -145,7 +145,7 @@ struct VerilogFrontend : public Frontend {
 		log("\n");
 		log("Note that the Verilog frontend does a pretty good job of processing valid\n");
 		log("verilog input, but has not very good error reporting. It generally is\n");
-		log("recommended to use a simulator (for example icarus verilog) for checking\n");
+		log("recommended to use a simulator (for example Icarus Verilog) for checking\n");
 		log("the syntax of the code, rather than to rely on read_verilog for that.\n");
 		log("\n");
 	}
@@ -345,7 +345,7 @@ struct VerilogDefaults : public Pass {
 		log("\n");
 		log("    verilog_defaults -clear");
 		log("\n");
-		log("Clear the list of verilog default options.\n");
+		log("Clear the list of Verilog default options.\n");
 		log("\n");
 		log("\n");
 		log("    verilog_defaults -push");

passes/cmds/connect.cc

@@ -50,7 +50,7 @@ struct ConnectPass : public Pass {
 		log("    connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr>\n");
 		log("\n");
 		log("Create a connection. This is equivalent to adding the statement 'assign\n");
-		log("<lhs-expr> = <rhs-expr>;' to the verilog input. Per default, all existing\n");
+		log("<lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing\n");
 		log("drivers for <lhs-expr> are unconnected. This can be overwritten by using\n");
 		log("the -nounset option.\n");
 		log("\n");

passes/cmds/select.cc

@@ -1061,7 +1061,7 @@ struct SelectPass : public Pass {
 		log("        like %%d but swap the roles of two top sets on the stack\n");
 		log("\n");
 		log("    %%c\n");
-		log("        create a copy of the top set rom the stack and push it\n");
+		log("        create a copy of the top set from the stack and push it\n");
 		log("\n");
 		log("    %%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n");
 		log("        expand top set <num1> num times according to the specified rules.\n");

passes/proc/proc_init.cc

@@ -93,7 +93,7 @@ struct ProcInitPass : public Pass {
 		log("\n");
 		log("    proc_init [selection]\n");
 		log("\n");
-		log("This pass extracts the 'init' actions from processes (generated from verilog\n");
+		log("This pass extracts the 'init' actions from processes (generated from Verilog\n");
 		log("'initial' blocks) and sets the initial value to the 'init' attribute on the\n");
 		log("respective wire.\n");
 		log("\n");

passes/techmap/extract.cc

@@ -361,7 +361,7 @@ struct ExtractPass : public Pass {
 		log("\n");
 		log("This pass looks for subcircuits that are isomorphic to any of the modules\n");
 		log("in the given map file and replaces them with instances of this modules. The\n");
-		log("map file can be a verilog source file (*.v) or an ilang file (*.il).\n");
+		log("map file can be a Verilog source file (*.v) or an ilang file (*.il).\n");
 		log("\n");
 		log("    -map <map_file>\n");
 		log("        use the modules in this file as reference. This option can be used\n");

passes/tests/test_autotb.cc

@@ -310,7 +310,7 @@ struct TestAutotbBackend : public Backend {
 		log("\n");
 		log("    test_autotb [options] [filename]\n");
 		log("\n");
-		log("Automatically create primitive verilog test benches for all modules in the\n");
+		log("Automatically create primitive Verilog test benches for all modules in the\n");
 		log("design. The generated testbenches toggle the input pins of the module in\n");
 		log("a semi-random manner and dumps the resulting output signals.\n");
 		log("\n");

passes/tests/test_cell.cc

@@ -556,7 +556,7 @@ struct TestCellPass : public Pass {
 		log("        print additional debug information to the console\n");
 		log("\n");
 		log("    -vlog {filename}\n");
-		log("        create a verilog test bench to test simlib and write_verilog\n");
+		log("        create a Verilog test bench to test simlib and write_verilog\n");
 		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design*)