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Docs: Fix code formatting 

Gets me everytime
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Krystine Sherwin 2024-08-22 10:03:59 +12:00
parent 36ad07e1d5
commit 0327ad97f2
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15
docs/source/yosys_internals/extending_yosys/build_verific.rst
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@ -55,8 +55,8 @@ ENABLE_VERIFIC_EDIF 0 EDIF support
ENABLE_VERIFIC_LIBERTY 0 Liberty file support
================================= ======= ===================================
To find the compile options used for a given Yosys build, call `yosys-config
--cxxflags`. This documentation was built with the following compile options:
To find the compile options used for a given Yosys build, call ``yosys-config
--cxxflags``. This documentation was built with the following compile options:
.. literalinclude:: /generated/yosys-config
:start-at: --cxxflags
@ -69,9 +69,10 @@ The following features, along with their corresponding Yosys build parameters,
are required for the Yosys-Verific patch:
* RTL elaboration with
* SystemVerilog with ENABLE_VERIFIC_SYSTEMVERILOG, and/or
* VHDL support with ENABLE_VERIFIC_VHDL.
* Hierarchy tree support and static elaboration with ENABLE_VERIFIC_HIER_TREE.
* SystemVerilog with ``ENABLE_VERIFIC_SYSTEMVERILOG``, and/or
* VHDL support with ``ENABLE_VERIFIC_VHDL``.
* Hierarchy tree support and static elaboration with
``ENABLE_VERIFIC_HIER_TREE``.
Please be aware that the following Verific configuration build parameter needs
to be enabled in order to create the fully supported build:
@ -93,8 +94,8 @@ Optional Verific features
The following Verific features are available with TabbyCAD and can be enabled in
Yosys builds:
* EDIF support with ENABLE_VERIFIC_EDIF, and
* Liberty file support with ENABLE_VERIFIC_LIBERTY.
* EDIF support with ``ENABLE_VERIFIC_EDIF``, and
* Liberty file support with ``ENABLE_VERIFIC_LIBERTY``.
Partially supported builds
~~~~~~~~~~~~~~~~~~~~~~~~~~