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Add write address to abc_scc_break of ECP5 dist RAM

This commit is contained in:
Eddie Hung 2019-06-28 09:45:48 -07:00
parent b9ddee0c87
commit 0318860b93
1 changed files with 1 additions and 1 deletions
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2
techlibs/ecp5/cells_sim.v
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@ -104,7 +104,7 @@ module PFUMX (input ALUT, BLUT, C0, output Z);
endmodule
// ---------------------------------------
(* abc_box_id=2, abc_scc_break="DI,WRE" *)
(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
module TRELLIS_DPR16X4 (
input [3:0] DI,
input [3:0] WAD,