Added Verilog support for "`default_nettype none"

frontends/ast/ast.cc

@@ -46,7 +46,7 @@ namespace AST {
 
 // instanciate global variables (private API)
 namespace AST_INTERNAL {
-	bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells;
+	bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
 	AstNode *current_ast, *current_ast_mod;
 	std::map<std::string, AstNode*> current_scope;
 	RTLIL::SigSpec *genRTLIL_subst_from = NULL;
@@ -836,11 +836,12 @@ static AstModule* process_module(AstNode *ast, bool defer)
 	current_module->lib = flag_lib;
 	current_module->noopt = flag_noopt;
 	current_module->icells = flag_icells;
+	current_module->autowire = flag_autowire;
 	return current_module;
 }
 
 // create AstModule instances for all modules in the AST tree and add them to 'design'
-void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer)
+void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire)
 {
 	current_ast = ast;
 	flag_dump_ast1 = dump_ast1;
@@ -852,6 +853,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
 	flag_lib = lib;
 	flag_noopt = noopt;
 	flag_icells = icells;
+	flag_autowire = autowire;
 
 	assert(current_ast->type == AST_DESIGN);
 	for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
@@ -897,6 +899,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
 	flag_lib = lib;
 	flag_noopt = noopt;
 	flag_icells = icells;
+	flag_autowire = autowire;
 	use_internal_line_num();
 
 	std::string para_info;
@@ -986,6 +989,7 @@ RTLIL::Module *AstModule::clone() const
 	new_mod->lib = lib;
 	new_mod->noopt = noopt;
 	new_mod->icells = icells;
+	new_mod->autowire = autowire;
 
 	return new_mod;
 }

frontends/ast/ast.h

@@ -238,13 +238,13 @@ namespace AST
 	};
 
 	// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
-	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool icells = false, bool ignore_redef = false, bool defer = true);
+	void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef, bool defer, bool autowire);
 
 	// parametric modules are supported directly by the AST library
 	// therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
 	struct AstModule : RTLIL::Module {
 		AstNode *ast;
-		bool nolatches, nomem2reg, mem2reg, lib, noopt, icells;
+		bool nolatches, nomem2reg, mem2reg, lib, noopt, icells, autowire;
 		virtual ~AstModule();
 		virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
 		virtual RTLIL::Module *clone() const;
@@ -265,7 +265,7 @@ namespace AST
 namespace AST_INTERNAL
 {
 	// internal state variables
-	extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells;
+	extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
 	extern AST::AstNode *current_ast, *current_ast_mod;
 	extern std::map<std::string, AST::AstNode*> current_scope;
 	extern RTLIL::SigSpec *genRTLIL_subst_from, *genRTLIL_subst_to, ignoreThisSignalsInInitial;

frontends/ast/genrtlil.cc

@@ -921,7 +921,10 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				RTLIL::Wire *wire = new RTLIL::Wire;
 				wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
 				wire->name = str;
+				if (flag_autowire)
 					log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
+				else
+					log_error("Identifier `%s' is implicitly declared at %s:%d and `default_nettype is set to none.\n", str.c_str(), filename.c_str(), linenum);
 				current_module->wires[str] = wire;
 			}
 			else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {

frontends/verilog/lexer.l

@@ -81,6 +81,18 @@ namespace VERILOG_FRONTEND {
 
 "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
 
+"`default_nettype"[ \t]+[^ \t\r\n/]+ {
+	char *p = yytext;
+	while (*p != 0 && *p != ' ' && *p != '\t') p++;
+	while (*p == ' ' || *p == '\t') p++;
+	if (!strcmp(p, "none"))
+		VERILOG_FRONTEND::default_nettype_wire = false;
+	else if (!strcmp(p, "wire"))
+		VERILOG_FRONTEND::default_nettype_wire = true;
+	else
+		frontend_verilog_yyerror("Unsupported default nettype: %s", p);
+}
+
 "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
 	frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
 }

frontends/verilog/parser.y

@@ -53,6 +53,7 @@ namespace VERILOG_FRONTEND {
 	struct AstNode *current_ast, *current_ast_mod;
 	int current_function_or_task_port_id;
 	std::vector<char> case_type_stack;
+	bool default_nettype_wire;
 }
 
 static void append_attr(AstNode *ast, std::map<std::string, AstNode*> *al)

frontends/verilog/preproc.cc

@@ -373,7 +373,6 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
 		}
 
 		if (tok == "`timescale") {
-			std::string name;
 			skip_spaces();
 			while (!tok.empty() && tok != "\n")
 				tok = next_token(true);

frontends/verilog/verilog_frontend.cc

@@ -256,6 +256,7 @@ struct VerilogFrontend : public Frontend {
 		AST::get_line_num = &frontend_verilog_yyget_lineno;
 
 		current_ast = new AST::AstNode(AST::AST_DESIGN);
+		default_nettype_wire = true;
 
 		FILE *fp = f;
 		std::string code_after_preproc;
@@ -279,7 +280,7 @@ struct VerilogFrontend : public Frontend {
 					child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
 		}
 
-		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer);
+		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);
 
 		if (!flag_nopp)
 			fclose(fp);

frontends/verilog/verilog_frontend.h

@@ -42,6 +42,9 @@ namespace VERILOG_FRONTEND
 
 	// this function converts a Verilog constant to an AST_CONSTANT node
 	AST::AstNode *const2ast(std::string code, char case_type = 0);
+
+	// state of `default_nettype
+	extern bool default_nettype_wire;
 }
 
 // the pre-processor