mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4 from alainmarcel/new_peepopts
Switch formal proof to use miter/sat
This commit is contained in:
commit
029c25536c
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@ -7,17 +7,21 @@ module top(a, b, s, y);
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input wire [3:0] b;
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input wire [3:0] b;
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input wire s;
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input wire s;
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output wire [3:0] y;
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output wire [3:0] y;
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assign y = s ? (a + b) : a;
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assign y = s ? (a + b) : a;
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endmodule
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endmodule
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EOF
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EOF
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check -assert
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check -assert
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equiv_opt -assert peepopt ;;;
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copy top orig
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design -load postopt
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cd top
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peepopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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log -pop
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log -pop
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log -header "Test basic s?(a+b):a pattern with intermediate var gets transformed (a,b module inputs)"
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log -header "Test basic s?(a+b):a pattern with intermediate var gets transformed (a,b module inputs)"
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log -push
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log -push
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design -reset
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design -reset
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@ -33,9 +37,15 @@ module top(a, b, s, y);
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endmodule
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endmodule
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EOF
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EOF
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check -assert
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check -assert
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equiv_opt -assert peepopt ;;;
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copy top orig
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design -load postopt
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cd top
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peepopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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log -pop
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log -pop
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log -header "Test basic s?(a+b):a pattern gets transformed (a is driven by a cell)"
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log -header "Test basic s?(a+b):a pattern gets transformed (a is driven by a cell)"
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@ -54,9 +64,15 @@ module top(a_, b, s, y);
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endmodule
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endmodule
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EOF
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EOF
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check -assert
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check -assert
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equiv_opt -assert peepopt
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copy top orig
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design -load postopt
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cd top
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peepopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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log -pop
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log -pop
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log -header "Test basic s?(a+b):a pattern gets transformed (b is driven by a cell, output consumed by a cell)"
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log -header "Test basic s?(a+b):a pattern gets transformed (b is driven by a cell, output consumed by a cell)"
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@ -78,9 +94,15 @@ module top(a, b_, f, s, y_);
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endmodule
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endmodule
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EOF
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EOF
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check -assert
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check -assert
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equiv_opt -assert peepopt
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copy top orig
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design -load postopt
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cd top
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peepopt
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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log -pop
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log -pop
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log -header "Test no transform when a+b has more fanouts (module output)"
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log -header "Test no transform when a+b has more fanouts (module output)"
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@ -98,9 +120,15 @@ module top(a, b, ab, s, y);
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endmodule
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endmodule
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EOF
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EOF
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check -assert
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check -assert
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equiv_opt -assert peepopt
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copy top orig
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design -load postopt
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cd top
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peepopt
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select -assert-none t:$add %co1 %a w:y %i
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select -assert-none t:$add %co1 %a w:y %i
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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log -pop
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log -pop
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log -header "Test no transform when a+b has more fanouts (single bit, cell)"
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log -header "Test no transform when a+b has more fanouts (single bit, cell)"
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@ -118,9 +146,19 @@ module top(a, b, s, y, z);
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endmodule
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endmodule
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EOF
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EOF
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check -assert
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check -assert
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equiv_opt -assert peepopt
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copy top orig
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design -load postopt
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cd top
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peepopt
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select -assert-none t:$add %co1 %a w:y %i
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select -assert-none t:$add %co1 %a w:y %i
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clean -purge
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cd
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miter -equiv -flatten -make_assert -make_outputs -ignore_gold_x top orig miter
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sat -verify -prove-asserts -show-ports -enable_undef miter
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# !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
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log Please fix all the designs below to use the miter/sat proof
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quit
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log -pop
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log -pop
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log -header "Test no transform when a+b width smaller than a's width"
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log -header "Test no transform when a+b width smaller than a's width"
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