mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4161 from YosysHQ/nak/add_sig_extract_asserts
SigSpec/SigChunk::extract(): assert offset/length are not out of range
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027cb31e9d
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@ -3686,6 +3686,9 @@ RTLIL::SigChunk::SigChunk(const RTLIL::SigBit &bit)
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RTLIL::SigChunk RTLIL::SigChunk::extract(int offset, int length) const
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{
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log_assert(offset >= 0);
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log_assert(length >= 0);
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log_assert(offset + length <= width);
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RTLIL::SigChunk ret;
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if (wire) {
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ret.wire = wire;
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@ -4398,6 +4401,9 @@ void RTLIL::SigSpec::remove(int offset, int length)
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RTLIL::SigSpec RTLIL::SigSpec::extract(int offset, int length) const
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{
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log_assert(offset >= 0);
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log_assert(length >= 0);
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log_assert(offset + length <= width_);
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unpack();
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cover("kernel.rtlil.sigspec.extract_pos");
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return std::vector<RTLIL::SigBit>(bits_.begin() + offset, bits_.begin() + offset + length);
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