mirror of https://github.com/YosysHQ/yosys.git
Keep gcc from complaining about uninitialized variables
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parent
0350074819
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022f570563
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@ -2102,9 +2102,9 @@ AstNode *AstNode::readmem(bool is_readmemh, std::string mem_filename, AstNode *m
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AstNode *block = new AstNode(AST_BLOCK);
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AstNode *block = new AstNode(AST_BLOCK);
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AstNode *meminit = nullptr;
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AstNode *meminit = nullptr;
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int next_meminit_cursor;
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int next_meminit_cursor=0;
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vector<State> meminit_bits;
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vector<State> meminit_bits;
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int meminit_size;
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int meminit_size=0;
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std::ifstream f;
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std::ifstream f;
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f.open(mem_filename.c_str());
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f.open(mem_filename.c_str());
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@ -79,7 +79,7 @@ void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
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Const initval = memory->parameters.at("\\INIT");
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Const initval = memory->parameters.at("\\INIT");
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RTLIL::Cell *last_init_cell = nullptr;
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RTLIL::Cell *last_init_cell = nullptr;
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SigSpec last_init_data;
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SigSpec last_init_data;
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int last_init_addr;
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int last_init_addr=0;
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for (int i = 0; i < GetSize(initval) && i/mem->width < (1 << abits); i += mem->width) {
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for (int i = 0; i < GetSize(initval) && i/mem->width < (1 << abits); i += mem->width) {
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Const val = initval.extract(i, mem->width, State::Sx);
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Const val = initval.extract(i, mem->width, State::Sx);
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