mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4753 from akashlevy/write_verilog_port_dump_fix
`write_verilog`: Fix `O(N^2)` port dumping to `O(N)`
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commit
020dd0a9e7
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@ -2332,21 +2332,17 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
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dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true);
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f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
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bool keep_running = true;
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int cnt = 0;
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for (int port_id = 1; keep_running; port_id++) {
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keep_running = false;
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for (auto wire : module->wires()) {
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if (wire->port_id == port_id) {
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if (port_id != 1)
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for (auto port : module->ports) {
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Wire *wire = module->wire(port);
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if (wire) {
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if (port != module->ports[0])
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f << stringf(", ");
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f << stringf("%s", id(wire->name).c_str());
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keep_running = true;
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if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;
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continue;
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}
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}
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}
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f << stringf(");\n");
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if (!systemverilog && !module->processes.empty()) {
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initial_id = NEW_ID;
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