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Merge pull request #4753 from akashlevy/write_verilog_port_dump_fix 

`write_verilog`: Fix `O(N^2)` port dumping to `O(N)`
This commit is contained in:
Martin Povišer 2024-11-17 23:42:23 +01:00 committed by GitHub
parent 81011ad926 ace558e90c
commit 020dd0a9e7
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1 changed files with 8 additions and 12 deletions
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12
backends/verilog/verilog_backend.cc
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@ -2332,21 +2332,17 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true); dump_attributes(f, indent, module->attributes, "\n", /*modattr=*/true);
f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str());
bool keep_running = true;
int cnt = 0; int cnt = 0;
for (int port_id = 1; keep_running; port_id++) { for (auto port : module->ports) {
keep_running = false; Wire *wire = module->wire(port);
for (auto wire : module->wires()) { if (wire) {
if (wire->port_id == port_id) { if (port != module->ports[0])
if (port_id != 1)
f << stringf(", "); f << stringf(", ");
f << stringf("%s", id(wire->name).c_str()); f << stringf("%s", id(wire->name).c_str());
keep_running = true;
if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++; if (cnt==20) { f << stringf("\n"); cnt = 0; } else cnt++;
continue; continue;
} }
} }
}
f << stringf(");\n"); f << stringf(");\n");
if (!systemverilog && !module->processes.empty()) { if (!systemverilog && !module->processes.empty()) {
initial_id = NEW_ID; initial_id = NEW_ID;