mirror of https://github.com/YosysHQ/yosys.git
SigMap performance improvement
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@ -242,7 +242,13 @@ struct SigMap
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void set(RTLIL::Module *module)
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void set(RTLIL::Module *module)
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{
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{
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clear();
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int bitcount = 0;
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for (auto &it : module->connections())
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bitcount += it.first.size();
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database.clear();
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database.reserve(bitcount);
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for (auto &it : module->connections())
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for (auto &it : module->connections())
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add(it.first, it.second);
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add(it.first, it.second);
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}
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}
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