mirror of https://github.com/YosysHQ/yosys.git
Various fixes/cleanups in alumacc and maccmap
This commit is contained in:
parent
124e759280
commit
014bb34e0e
|
@ -443,7 +443,6 @@ struct AlumaccWorker
|
||||||
n->alu_cell->setPort("\\X", module->addWire(NEW_ID, SIZE(n->y)));
|
n->alu_cell->setPort("\\X", module->addWire(NEW_ID, SIZE(n->y)));
|
||||||
n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, SIZE(n->y)));
|
n->alu_cell->setPort("\\CO", module->addWire(NEW_ID, SIZE(n->y)));
|
||||||
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
|
n->alu_cell->fixup_parameters(n->is_signed, n->is_signed);
|
||||||
log_cell(n->alu_cell);
|
|
||||||
|
|
||||||
for (auto &it : n->cmp)
|
for (auto &it : n->cmp)
|
||||||
{
|
{
|
||||||
|
|
|
@ -208,7 +208,17 @@ struct MaccmapWorker
|
||||||
|
|
||||||
log_assert(tree_sum_bits.empty());
|
log_assert(tree_sum_bits.empty());
|
||||||
|
|
||||||
return module->Add(NEW_ID, summands.front(), summands.back());
|
RTLIL::Cell *c = module->addCell(NEW_ID, "$alu");
|
||||||
|
c->setPort("\\A", summands.front());
|
||||||
|
c->setPort("\\B", summands.back());
|
||||||
|
c->setPort("\\CI", RTLIL::S0);
|
||||||
|
c->setPort("\\BI", RTLIL::S0);
|
||||||
|
c->setPort("\\Y", module->addWire(NEW_ID, width));
|
||||||
|
c->setPort("\\X", module->addWire(NEW_ID, width));
|
||||||
|
c->setPort("\\CO", module->addWire(NEW_ID, width));
|
||||||
|
c->fixup_parameters();
|
||||||
|
|
||||||
|
return c->getPort("\\Y");
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue