riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix issue with part of PI being 1'bx

This commit is contained in:
Eddie Hung 2019-06-20 17:29:45 -07:00
parent f11c9a419b
commit 014606affe
2 changed files with 11 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
frontends/aiger/aigerparse.cc
View File

@ -947,11 +947,13 @@ void AigerReader::post_process()
if (other_wire) { if (other_wire) {
other_wire->port_input = false; other_wire->port_input = false;
other_wire->port_output = false; other_wire->port_output = false;
if (wire->port_input)
module->connect(other_wire, SigSpec(wire, i));
else
module->connect(SigSpec(wire, i), other_wire);
} }
if (wire->port_input && other_wire)
module->connect(other_wire, SigSpec(wire, i));
else
// Since we skip POs that are connected to Sx,
// re-connect them here
module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx));
} }
} }

5
tests/simple_abc9/abc9.v
View File

@ -262,3 +262,8 @@ endmodule
module abc9_test025(input [3:0] i, output [3:0] o); module abc9_test025(input [3:0] i, output [3:0] o);
abc9_test024_sub a(i[2:1], o[2:1]); abc9_test024_sub a(i[2:1], o[2:1]);
endmodule endmodule
module abc9_test026(output [3:0] o, p);
assign o = { 1'b1, 1'bx };
assign p = { 1'b1, 1'bx, 1'b0 };
endmodule