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abc9_ops: -prep_xaiger exclude (* abc9_keep *) wires from toposort
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@ -719,8 +719,10 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
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bit_users[bit].insert(cell->name);
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if (cell->output(conn.first) && !abc9_flop)
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for (auto bit : sigmap(conn.second))
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bit_drivers[bit].insert(cell->name);
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for (const auto &chunk : conn.second.chunks())
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if (!chunk.wire->get_bool_attribute(ID::abc9_keep))
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for (auto b : sigmap(SigSpec(chunk)))
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bit_drivers[b].insert(cell->name);
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}
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toposort.node(cell->name);
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}
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