riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Initialize RTLIL::Const from std::vector<bool>

This commit is contained in:
Clifford Wolf 2014-09-19 15:50:55 +02:00
parent 309623ff17
commit 00964f2f61
2 changed files with 9 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
kernel/rtlil.cc
View File

@ -65,6 +65,13 @@ RTLIL::Const::Const(RTLIL::State bit, int width)
bits.push_back(bit); bits.push_back(bit);
} }
RTLIL::Const::Const(const std::vector<bool> &bits)
{
flags = RTLIL::CONST_FLAG_NONE;
for (auto b : bits)
this->bits.push_back(b ? RTLIL::S1 : RTLIL::S0);
}
bool RTLIL::Const::operator <(const RTLIL::Const &other) const bool RTLIL::Const::operator <(const RTLIL::Const &other) const
{ {
if (bits.size() != other.bits.size()) if (bits.size() != other.bits.size())

3
kernel/rtlil.h
View File

@ -428,7 +428,8 @@ struct RTLIL::Const
Const(std::string str); Const(std::string str);
Const(int val, int width = 32); Const(int val, int width = 32);
Const(RTLIL::State bit, int width = 1); Const(RTLIL::State bit, int width = 1);
Const(std::vector<RTLIL::State> bits) : bits(bits) { flags = CONST_FLAG_NONE; }; Const(const std::vector<RTLIL::State> &bits) : bits(bits) { flags = CONST_FLAG_NONE; };
Const(const std::vector<bool> &bits);
bool operator <(const RTLIL::Const &other) const; bool operator <(const RTLIL::Const &other) const;
bool operator ==(const RTLIL::Const &other) const; bool operator ==(const RTLIL::Const &other) const;