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Add LUTRAM delays

This commit is contained in:
Eddie Hung 2019-08-20 13:53:38 -07:00
parent 505d062daf
commit 0079e9b4a6
1 changed files with 6 additions and 3 deletions
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9
techlibs/xilinx/cells_sim.v
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@ -289,7 +289,8 @@ endmodule
(* abc_box_id = 5 *)
module RAM32X1D (
output DPO, SPO,
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc_arrival=1472 *) output DPO, SPO,
(* abc_scc_break *) input D,
input WCLK,
(* abc_scc_break *) input WE,
@ -309,7 +310,8 @@ endmodule
(* abc_box_id = 6 *)
module RAM64X1D (
output DPO, SPO,
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc_arrival=1472 *) output DPO, SPO,
(* abc_scc_break *) input D,
input WCLK,
(* abc_scc_break *) input WE,
@ -329,7 +331,8 @@ endmodule
(* abc_box_id = 7 *)
module RAM128X1D (
output DPO, SPO,
// Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905
(* abc_arrival=1472 *) output DPO, SPO,
(* abc_scc_break *) input D,
input WCLK,
(* abc_scc_break *) input WE,