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Move abc9 from yosys-0.8 to yosys-0.9 in CHANGELOG

This commit is contained in:
Eddie Hung 2019-07-01 09:44:53 -07:00
parent 7be8551c8d
commit 0067dc44f3
1 changed files with 11 additions and 5 deletions
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16
CHANGELOG
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@ -3,6 +3,17 @@ List of major changes and improvements between releases
=======================================================
Yosys 0.9 .. Yosys 0.9-dev
--------------------------
* Various
- Added "write_xaiger" backend
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental)
Yosys 0.8 .. Yosys 0.8-dev
--------------------------
@ -26,11 +37,6 @@ Yosys 0.8 .. Yosys 0.8-dev
- Added "synth_xilinx -nocarry"
- Added "synth_xilinx -nowidelut"
- Added "synth_ecp5 -nowidelut"
- Added "write_xaiger" backend
- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
- Added "synth_xilinx -abc9" (experimental)
- Added "synth_ice40 -abc9" (experimental)
- Added "synth -abc9" (experimental)
- "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
- Fixed sign extension of unsized constants with 'bx and 'bz MSB